IP verification Engineer
1 week ago
Job Description Job Details Job Description: Designs, develops, validates, and/or debugs software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients. Key Responsibilities - Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans. - Develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology). - Create and implement directed and random test cases and test sequences to exercise design functionality and uncover potential bugs. - Develop verification components, including drivers, monitors, scoreboards, and checkers. - Utilize SystemVerilog Assertions (SVA) and formal verification methods to enhance bug detection and verify complex properties. - Execute simulation regressions, debug test failures, analyze root causes, and work with designers to implement corrective measures. - Define and track functional and code coverage metrics to ensure verification completeness and drive coverage closure. - Develop automation scripts and infrastructure using languages like Python or Perl to improve verification efficiency and flows. - Participate in technical reviews of specifications, design documents, and test plans, providing valuable input and feedback. Qualifications - Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. - 5+ years of experience in ASIC or FPGA design verification. - Expertise in Hardware Description Languages (HDL) like Verilog or VHDL and Hardware Verification Languages (HVL) such as SystemVerilog. - Strong hands-on experience in developing UVM-based testbenches and verification components. - Proficiency in modern verification methodologies, including coverage-driven verification (CDV) and assertion-based verification (ABV). - Familiarity with industry-standard protocols such as AMBA (AXI, ACE, CHI, APB), PCIe, or Ethernet is a plus. - Experience with simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa). - Strong scripting skills in Python, Perl, or Tcl for automation and data analysis. - Excellent analytical, problem-solving, and debugging skills. - Strong communication skills and the ability to work effectively in a collaborative, cross-functional team environment. Job Type Regular Shift Shift 1 (India) Primary Location: Bengaluru, Karnataka, India Additional Locations: Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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IP verification Engineer
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Bengaluru, Karnataka, India FiniteHR Consulting Full time ₹ 5,00,000 - ₹ 15,00,000 per yearCompany Description Client of FiniteHR, IT Embedded Company Job Description Our Client SeviTech is looking for IP Verification Engineer.About our Client: Job Designation: IP Verification Engineer.Job Location: BangaloreJob Type: Permanent IP Verification:For the position of IP Verification Engineer the following qualifications must be met:5+ years of...
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Bengaluru, Karnataka, India FiniteHR Consulting Full time ₹ 40,00,000 - ₹ 1,20,00,000 per yearCompany Description Finite HR Consulting Job Description Our Client Sevitech is looking for IP Verification Engineer.About our Client: Job Designation: IP Verification Engineer.Job Location: BangaloreJob Type: Permanent IP Verification:Job description:• You will be part of an IP Verification Team leading to first pass Silicon success.• You will be...
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Bengaluru, India ACL Digital Full timeSenior Verification EngineerEmail: prabhu.p@acldigital.comWhatsApp: 8754387484Location: Bangalore (Hybrid — 2 days/week onsite)Notice Period: Less than 30 days onlyExperience - 5 - 30 Years📌 JD 1 — Requirement: 1 RequirementRole: Senior Design Verification Engineer (15+ Years Experience) (Designation Based on the Final Discussion will decide with...
