Digital Verification Leader
3 weeks ago
Job Description Senior Design Verification Engineer We are seeking talented Design Verification Engineers with proven expertise in industry-standard protocols such as PCIe and CXL. You will play a key role in the functional verification of designs, from developing block-level and system-level verification plans to writing test sequences, executing tests, and collecting and closing coverage. Responsibilities - Develop and execute block-level and system-level verification plans. - Write and execute test sequences and collect and close coverage. - Collaborate with RTL designers to debug failures and refine verification processes. - Utilize coding and protocol expertise to contribute to functional verification. - Develop user-controlled random constraints in transaction-based verification methodologies. - Write assertions, cover properties, and analyze coverage data. - Create VIP abstraction layers for sequences to simplify and scale verification deployments. - Basic Qualifications - Minimum of 8 years experience in supporting or developing complex SoC/silicon products for server, storage, and/or networking applications. - Strong academic and technical background in Electrical Engineering or Computer Engineering (bachelor's degree required, master's preferred). - Professional attitude with the ability to prioritize tasks, prepare for customer meetings, and work independently with minimal guidance. - Knowledge of industry-standard simulators, revision control systems, and regression systems. - Entrepreneurial, open-minded behavior and a can-do attitude, with a focus on customer satisfaction. - Required Experience - Interpreting PCIe/CXL standard protocol specifications to develop and execute verification plans in simulation environments. - Experience using Verification IPs from third-party vendors for PCIe/CXL, focusing on Gen3 or above. - Ability to independently develop test plans and sequences in UVM to generate stimuli. - Experience writing assertions, cover properties, and analyzing coverage data. - Developing VIP abstraction layers for sequences to simplify and scale verification deployments. - Preferred Experience - Expertise in verifying Physical Layer, Link Layer, and Transaction Layer of PCIe/CXL protocols, including compliance on PCIe/CXL EP/RC. - Experience with buffering and queuing with QoS on complex NOC-based SoCs. - Analyzing performance at the system level on switching fabrics.
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Functional Verification Engineer
3 weeks ago
Bengaluru, India ACL Digital Full timeJob Description Lead Functional Verification Engineer Experience: 6+ Years Location: Bangalore Job Description: - Lead verification activities for complex CPU cores, memory subsystems, and high-speed PCIe IPs. - Define verification strategy, test plan, and coverage goals based on architecture and spec reviews. - Build and maintain advanced UVM-based...
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Senior Design Verification Engineers
2 weeks ago
india ACL Digital Full timeHi All,ACL Digital is looking for "Senior Design Verification Engineers"Exp Level: 4+ years Notice period: Immediate to 30 days Location: Bangalore and HyderabadJob Description: Must have good knowledge on the verification flows Excellent hands-on debug skills and problem solving attitude. Experience of working in complex test-bench/model in Verilog, System...
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Noc verification engineer
2 weeks ago
Bengaluru, India ACL Digital Full timeNo C Verification EngineerExperience : 7 to 14 YearsKey Responsibilities:Develop UVM-based verification environments for No C/IP blocks such as Flex No C, GNOC, or custom No C fabrics.Define and implement test plans, coverage models, scoreboards, monitors, and checkers for coherent and non-coherent traffic.Integrate and verify IPs like AXI4, CHI-B/C/E, PCIe,...
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NoC Verification Engineer
1 week ago
Bengaluru, India ACL Digital Full timeNoC Verification EngineerExperience: 7 to 14 YearsKey Responsibilities:Develop UVM-based verification environments for NoC/IP blocks such as FlexNoC, GNOC, or custom NoC fabrics.Define and implement test plans, coverage models, scoreboards, monitors, and checkers for coherent and non-coherent traffic.Integrate and verify IPs like AXI4, CHI-B/C/E, PCIe, and...
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NoC Verification Engineer
4 days ago
Bengaluru, India ACL Digital Full timeNoC Verification EngineerExperience: 7 to 14 YearsKey Responsibilities:Develop UVM-based verification environments for NoC/IP blocks such as FlexNoC, GNOC, or custom NoC fabrics.Define and implement test plans, coverage models, scoreboards, monitors, and checkers for coherent and non-coherent traffic.Integrate and verify IPs like AXI4, CHI-B/C/E, PCIe, and...
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Rtl Design Verification Engineer
2 weeks ago
Bengaluru, India ACL Digital Full timeSOC RTL Design Verification Experience: 4 to 10 Years Location: Bangalore Key Responsibilities: - Verification of SOC RTL (This is a DV Req) : FW-HW co-verification at SOC level, good understanding of SOC boot flow, integration level verification - Development and verification of post-si validation sequences using C/C++ - Create methodology-based (UVM)...
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RTL Design Verification Engineer
2 weeks ago
Bengaluru, India ACL Digital Full timeSOC RTL Design Verification Experience : 4 to 10 Years Location : Bangalore Key Responsibilities: • Verification of SOC RTL (This is a DV Req) : FW-HW co-verification at SOC level, good understanding of SOC boot flow, integration level verification • Development and verification of post-si validation sequences using C/C++ • Create methodology-based...
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RTL Design Verification Engineer
1 day ago
Bengaluru, India ACL Digital Full timeSOC RTL Design Verification Experience : 4 to 10 Years Location : Bangalore Key Responsibilities: • Verification of SOC RTL (This is a DV Req) : FW-HW co-verification at SOC level, good understanding of SOC boot flow, integration level verification • Development and verification of post-si validation sequences using C/C++ • Create methodology-based...
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RTL Design Verification Engineer
2 weeks ago
Bengaluru, India ACL Digital Full timeSOC RTL Design VerificationExperience: 4 to 10 YearsLocation: BangaloreKey Responsibilities:• Verification of SOC RTL (This is a DV Req) : FW-HW co-verification at SOC level, good understanding of SOC boot flow, integration level verification• Development and verification of post-si validation sequences using C/C++• Create methodology-based (UVM)...
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RTL Design Verification Engineer
2 weeks ago
Bengaluru, India ACL Digital Full timeSOC RTL Design VerificationExperience: 4 to 10 YearsLocation: BangaloreKey Responsibilities:• Verification of SOC RTL (This is a DV Req) : FW-HW co-verification at SOC level, good understanding of SOC boot flow, integration level verification• Development and verification of post-si validation sequences using C/C++• Create methodology-based (UVM)...
