Principal Design Verification Engineer

Job Description

About Analog Devices

Analog Devices, Inc. (NASDAQ:) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible. Learn more atand onand.

Principal Engineer, Design Verification
The Engineering Enablement team provides industry-leading tools, methodologies, and support to accelerate product development across the company. This position is part of the Digital Systems IP team within the Engineering Enablement organization. The IP team builds, curates and guides the development of IP across ADI.

Were seeking a highly experienced, seasoned DV expert with experience in leading DV efforts for verification of different IP components, subsystems from scratch.

About the role
In this position the successful candidate will be exposed to the entire product lifecycle from concept phase, through design, verification, implementation, and release of IP to various product teams. They will collaborate with the wider ADI technical community, which affords an opportunity to work with many business units in ADI with exposure to many technologies and products. This is a senior role with the opportunity to create real impact within the organization and build a promising career.

Responsibilities
Verification of complex Digital designs and sub-systems using leading edge verification methodologies.
Architecting a unified verification testbench environment
Defining verification strategy, testplans, tests and verification methodology for chip-level verification. Working with the design team in generating test-plans and closure of code and functional coverage
Technically mentoring verification engineers on SoC Verification responsible for block/IP-level DV

Continuous interaction with Design, Architecture and Firmware teams
Tracking and management of design verification improvements

Required Qualifications

Bachelor's or Masters degree, in Engineering (Electronic Engineering) or equivalent.
15 years ASIC design verification or related work experience.

Leadership skills enabling one to define and implement a verification strategy
Demonstrated ability to communicate with peers, managers, and project stakeholders effectively using both verbal and written communications
Proficient in developing unit and SoC level test benches using UVM
Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology, formal verification
Behavioral modeling of analog blocks, System Verilog Real-Number Modeling, behavioral model validation and mixed-signal simulators like Cadence Xcelium
Working with processors
Gate Level Simulation (GLS) verification flow for SoC verification.
Verilog, C/C++, System C, Java, TCL/Perl/Python/shell-scripting
Experience in Property Specification Language (PSL), Matlab (including for co-simulation and HDL generation) and digital signal processing would be a plus
Low power methodologies such as CPF/UPF
Excellent interpersonal and communication skills and the dream to take on diverse challenges
Self-motivated and enthusiastic

Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: 1st Shift/Days

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