Design Verification Engineering Manager

Lead an Application-Specific Integrated Circuit ASIC design verification team including managers responsible for various processing blocks within a System-on-Chip SOC Manage the development and execution of verification plans drive innovative verification methodologies and ensure both functional and code coverage closure Collaborate closely with Architecture Software Firmware Design Modeling Emulation and Post-Silicon Validation teams to support silicon architecture and micro-architecture development ensuring seamless integration and successful project outcomes Design Verification Engineering Manager Responsibilities Collaborate with cross-functional teams including executives managers and individual contributors development engineers capacity planners supply chain experts to drive business objectives Develop and maintain the overall silicon strategy aligned with the corporation s Long Range Plan objectives Partner with IP development teams to identify select and license soft and hard IP Lead a team of ASIC engineers through hiring training and guidance to ensure on-time and on-budget product delivery Analyze and review SOWs from vendors supporting documentation and requirements sets to meet internal customer needs Support engineering teams in defining debugging implementing and delivering total solutions around purpose-built ASICs Establish and maintain key performance indicators KPI for areas of responsibility Partner with technical program management and supply chain teams to manage external development partners suppliers and vendors Provide support to design verification team managers Minimum Qualifications B S or M S degree in Computer Engineering Electrical Engineering or a relevant technical field or equivalent practical experience 12 years of ASIC SoC design verification experience 7 years of people management experience including leading managers and experienced Individual contributors In depth understanding of design verification tools such as Synopsys VCS Cadence Xcelium Simulator Verdi JasperGold or VC Formal Proven track record of first-pass success in ASIC development Experience managing multiple projects prioritizing tasks and collaborating with stakeholders Skilled in Universal Verification Methodology UVM constrained random test bench development and delivery Capacity to interpret functional specs and create comprehensive test plans Experience managing managers who support small to mid-sized teams Preferred Qualifications In-depth knowledge of at least one area Video coding standards Signal processing algorithms Neural networks and machine learning concepts Other neural network development frameworks Experience with formal verification techniques and methodologies Hands-on experience with complex subsystems including memory Low Power Double Data Rate High Bandwidth Memory cache Peripheral Component Interconnect Express and network-on-chip with a focus on performance verification About Meta Meta builds technologies that help people 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