Formal Verification Intern
2 weeks ago
Formal Verification Engineer at Synopsys, you will be responsible for formally verifying complex design IPs. Synopsys IP Group has a strong formal verification methodology that enables hardware verification engineers to use FV tools and techniques successfully on complex and/or critical RTL logic. The job involves very close interaction with the designers, architects, verification engineers and Synopsys&aposs Tool Development Group to drive verification projects.
Expectations from the candidate
- Help decide on the best applications of formal verification techniques to various parts of the design.
- Review functional and micro-architectural specifications, define the scope for formal verification, and create high-quality formal verification testplans to sign-off on the corresponding design implementation.
- Build formal verification testbenches, code assertions and constraints, and apply abstraction techniques to converge the targeted properties or to achieve reasonable proof-depth.
- Apply formal coverage techniques for analysing over-constraints and for measuring functional coverage.
Required Skills
- Pursuing or completed BTech/ MTech degree
- Good understanding of hardware micro-architecture and design
- Proficiency in HDLs like Verilog, SystemVerilog
- Familiarity with SystemVerilog Assertions (SVA) and basic concepts of formal property verification
- Good debugging and problem-solving skills
- Scripting knowledge (Python/Perl/shell)
- Good interpersonal and communication skills and dream to work as a great team member
Good To Have Skills
- Academic projects related to formal verification or digital design verification
- Exposure to formal verification tools like VCFormal, Jasper, Yosys etc
- Knowledge of protocols like AXI, CHI, PCIe, DDR, etc
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