Design Verification Engineer

4 weeks ago

Bengaluru India Capgemini Engineering Full time

Job Description

We are looking for more than 5years of experience.

JOB Description

- Total experience (5 -7 years) with SOC GLS experience of minimum 3+ years
- Hands on experience in GLS (Zero Delay, SDF, PAGLS)
- Excellent debugging skills and fixing issues
- Knowledge in SV/UVM and test bench flow
- Good experience in EDA tools such as Synopsys Verdi, Cadence NC Sim.
- Understanding of SOC Architecture

Education Qualification:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field

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