3 Days Left) ASIC Physical Design, Sr Engineer

Job Description

Alternate Job Titles:

- ASIC Physical Design Engineer
- Place & Route Engineer
- Sr. Physical Design Specialist

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and detail-oriented engineer with a strong background in ASIC physical design and a keen interest in advancing semiconductor technology. You thrive in collaborative, fast-paced environments and are motivated by technical challenges that push the boundaries of whats possible in chip design. With your foundational education in electronics or electrical engineering, you have honed a solid understanding of CMOS and submicron ASIC flows, working on advanced technology nodes such as 28nm, 16nm, 14nm, 10nm, and 7nm. You possess hands-on experience with industry-leading EDA tools, including Synopsys ICC-II/FC, Design Compiler, PrimeTime, and Cadence Innovus, and are adept at developing, optimizing, and verifying robust ASIC design flows.

Your curiosity drives you to stay on top of the latest methodologies, and your analytical mindset ensures you can solve complex problems with innovative solutions. You are comfortable taking ownership of tasks, whether its developing flows, performing timing analysis, or releasing production views for IP. You communicate clearly, collaborate effectively, and are committed to delivering high-quality results with attention to every detail. You believe in continuous improvement, proactively seeking ways to optimize power, performance, and area (PPA) while maintaining the highest standards of quality. Most importantly, you are excited about making an impact in a global team that values diversity, learning, and technological excellence.

What Youll Be Doing:

- Developing and optimizing ASIC design flows to build and verify standard cell libraries, ensuring the best possible Power, Performance, and Area (PPA) with uncompromised quality.
- Creating and maintaining Place & Route (P&R) methodologies using industry-standard tools such as Synopsys ICC-II/FC and Cadence Innovus.
- Releasing P&R production views for IP, ensuring readiness for downstream design and integration teams
- Conducting thorough physical verification (DRC/LVS), timing analysis (STA), and addressing design closure challenges across advanced technology nodes.
- Collaborating with cross-functional teams to integrate design flows, improve automation, and resolve technical issues throughout the ASIC lifecycle.
- Implementing and validating low-power design concepts using UPF/CPF formats, and ensuring robust power analysis and planning.
- Generating and managing technology files, library views (Milkyway, NDM), and deliverables such as LEF, DEF, GDS for standard cell libraries.

The Impact You Will Have:

- Enable the creation of high-performance, energy-efficient silicon chips that power next-generation applications and devices.
- Drive improvements in PPA and overall design quality, directly influencing customer satisfaction and product competitiveness.
- Ensure timely and robust release of IP production views, accelerating time-to-market for Synopsys customers.
- Advance the state-of-the-art in physical design methodologies, contributing to Synopsys leadership in the semiconductor industry.
- Collaborate cross-functionally to share best practices and foster a culture of continuous improvement and innovation.
- Support the successful deployment of Synopsys tools and flows in real-world customer projects, reinforcing our reputation for technical excellence.

What Youll Need:

- Bachelors or Masters degree in Electronics or Electrical Engineering (or equivalent) from a reputed university.
- 1-2 years experience in ASIC design, with hands-on exposure to advanced process nodes (28nm, 16nm, 14nm, 10nm, 7nm) and multiple foundries.
- Strong understanding of CMOS, ASIC flow in submicron nodes, and expertise in Place & Route, physical verification (DRC/LVS), and timing analysis (STA).
- Proficiency with Synopsys (ICC-II/FC, Design Compiler, PrimeTime) and Cadence (Innovus, RC/Genus) EDA tools.
- Experience with all stages of the ASIC design flow, including Synthesis, DFT, timing analysis, floor planning, power planning, CTS, ECO flow, STA, and power analysis.
- Good grasp of low power design concepts, UPF/CPF formats, and standard cell library view generation processes (Milkyway, NDM).

Who You Are:

- Analytical thinker with strong problem-solving skills and meticulous attention to detail.
- Effective communicator, able to articulate complex technical concepts to diverse audiences.
- Collaborative team player who thrives in a multicultural and multidisciplinary environment.
- Self-motivated, adaptable, and eager to learn new technologies and methodologies.
- Proactive in identifying areas for improvement and driving innovative solutions.

The Team Youll Be A Part Of:

Youll join a dynamic, inclusive team of physical design and ASIC implementation experts dedicated to developing world-class design flows and methodologies. Our team collaborates closely with IP development, CAD, and validation groups, sharing knowledge and driving best practices across the organization. We value open communication, continuous learning, and a passion for technical excellence, and we are committed to supporting each others growth and success.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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