Senior Design Verification Engineer

2 weeks ago


Hyderabad, Telangana, India WiSig Networks Full time
Job Description

About the Role:

You will be responsible for developing advanced verification environments, leading cross-functional technical initiatives, and mentoring team members while ensuring the highest quality standards in our ASIC designs.

The candidate should come up with test plans and test cases in order to achieve 100% code coverage and functional coverage.

Responsibilities

Job Location: Hyderabad

Exp 5 +Years

Design and implement advanced System Verilog/UVM verification infrastructures

Lead verification planning and execution for complex ASIC projects

Expert-level System Verilog, UVM, and object-oriented programming skills

Able to build and set up scalable simulation / verification environments

Experience in ASIC/FPGA verification using System Verilog.

Experience in scripting, such as TCL, Perl, Bash and python to automate the verification

methodologies and flows.

Able to build and set up scalable simulation / verification environments.

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