▷ Apply Now: Asic Engineer, Implementation

Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization We are looking for individuals with experience in front-end implementation from RTL to netlist including RTL Lint CDC analysis timing constraints synthesis to build efficient System on Chip SoC and IP for data center applicationASIC Engineer Implementation ResponsibilitiesRun Logic Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing Area Power Debug the timing area congestion issues and work with RTL Physical designers to resolve them Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities Run Formal Verification checks between RTL and Gate level netlist and debug the aborts inconclusive and Logic Equivalency failures Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC Perform Flat and Hierarchical Reset Domain crossing Checks Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC Analyze the inter-block timing and come up with IO budgets for the various partition blocks Develop Power Intent Specification in UPF for the multi-Vdd designs Developing Automation scripts and Methodology for all FE-tools including Lint CDC RDC Synthesis STA Power Work closely with the Design Engineers DV Engineers Emulation Engineers in supporting them with the handoff tasks Interact with Physical Design Engineers and provide them with timing congestion feedback Minimum QualificationsBachelor s degree in Computer Science Computer Engineering relevant technical field or equivalent practical experience 5 years of experience in Design Integration and Front-End Implementation Experience with RTL Synthesis and design optimization for Power Performance Area Knowledge of front-end and back-end ASIC tools Experience with RTL design using SystemVerilog or other HDL Experience managing multiple design releases and working with cross functional teams to support and debug timing area power issues Experience with EDA tools and scripting languages Python TCL used to build tools and flows for complex environments Experience with communicating across functional internal teams and vendors Preferred QualificationsKnowledge of Clock Domain Crossing Reset Domain Crossing LEC Synthesis Background Timing Constraints Development Floorplanning and STA Experience Knowledge of RTL coding using Verilog System Verilog Knowledge of Timing physical libraries SRAM Memories Experience with Power Performance Area Analysis and techniques for reducing power Knowledge of Low power design Experience with Design Compiler Spyglass PrimeTime Formality or equivalent tools Scripting and programming experience using Perl Python TCL and Make LocationsAbout MetaMeta builds technologies that help people connect find communities and grow businesses When Facebook launched in 2004 it changed the way people connect Apps like Messenger Instagram and WhatsApp further empowered billions around the world Now Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today-beyond the constraints of screens the limits of distance and even the rules of physics Equal Employment Opportunity and Affirmative ActionMeta is proud to be an Equal Employment Opportunity and Affirmative Action employer We do not discriminate based upon race religion color national origin sex including pregnancy childbirth reproductive health decisions or related medical conditions sexual orientation gender identity gender expression age status as a protected veteran status as an individual with a disability genetic information political views or activity or other applicable legally protected characteristics You may view our Equal Employment Opportunity notice Meta is committed to providing reasonable support called accommodations in our recruiting processes for candidates with disabilities long term conditions mental health conditions or sincerely held religious beliefs or who are neurodivergent or require pregnancy-related support If you need support please reach out to Related Job OpeningsBangalore IndiaBangalore IndiaBangalore IndiaBangalore IndiaBangalore IndiaHyderabad India 1 MoreCareersFollow usCareer programsTeamsWorking at MetaMy accountAbout usEqual Employment Opportunity and Affirmative ActionMeta is proud to be an Equal Employment Opportunity and Affirmative Action employer We do not discriminate based upon race religion color national origin sex including pregnancy childbirth reproductive health decisions or related medical conditions sexual orientation gender identity gender expression age status as a protected veteran status as an individual with a disability genetic information political views or activity or other applicable legally protected characteristics You may view our Equal Employment Opportunity notice Meta is committed to providing reasonable support called accommodations in our recruiting processes for candidates with disabilities long term conditions mental health conditions or sincerely held religious beliefs or who are neurodivergent or require pregnancy-related support If you need support please reach out to