Lead Design Engineer

4 weeks ago

Bengaluru, Karnataka, India Cadence Design Systems Full time
Job Description

Job description

- The responsibility primarily entails performing pre and post silicon Physical Layer Electrical Validation on Cadences High Speed SERDES IP.

Activities include

- Designing the hardware and software infrastructure required to enable validation (Test PCBs, Controlling FPGA platforms, Labview/Python automation)
- Implementing test suites for rigorously testing the compliance of the IP to Physical Layer Electrical specifications
- Debugging Silicon issues and generating high quality test reports for customers

Minimum Qualifications:

- BE/BTECH/ME/MTECH Equivalent Degree
- 3-4 years (with Btech) or 1-2 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation
- Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, Ethernet, SRIO, JESD204, DDRIO
- Hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzers, Bit Error Rate Testers (BERT)

Preferred Qualifications:

- Candidates are expected to be passionate about analog and digital electronic circuit design aspects as we'll as signal processing related aspects
- 1-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping is a plus
- Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug
- Familiarity with RTL coding for FPGA, Labview, Python, C/C++, TCL

Role:Hardware Architect

Industry Type:IT Services & Consulting

Department:Engineering - Hardware & Networks

Employment Type:Full Time, Permanent

Role Category:Hardware

Education

UG:Any Graduate

PG:Any Postgraduate

Key Skills

AutomationC++AerospaceUSBAnalogSOCSystem designLabviewAutomotivePython

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