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2 weeks ago
Siemens EDA is a global technology leader in Electronic Design Automation software Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip board and system design Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs The detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results at a competitive runtime This role is based in Bangalore But youll also get to visit other locations in India and globe so youll need to go where this job takes you In return youll get the chance to work with teams impacting entire cities countries and the shape of things to come This is your role Lead a Team of Engineers working on solving the latest design challenged in Logic Synthesis Collaborate with RnD and drive the roadmap for next generation RTL2GDSII solution Work with design community in solving critical designs problems to achieve desired performance area and power targets Deployment of Synthesis solution with various customers working on cutting edge technologies 7nm and forward Develop deploy training and technical support to customers using Siemens EDA tools We dont need superheroes just superminds Typically requires minimum of 2-5 years of experience in Logic Synthesis flows Proficiency in Verilog System Verilog VHDL Strong knowledge of RTL2GDSII flow with strong fundamentals in digital design implementation Prior experience in IC digital design flows and front-end EDAT tools including Synthesis DFT Formal Verification Logic Equivalence Checks Hands-on experience using commercial synthesis tools like Synopsys-DC FC Cadence-Genus is a must Experience with advance technology nodes 7nm and below Hands-on experience in debug deliver solutions to critical design issues related to synthesis TCL Perl or Python scripting is a plus Self-motivated team player with a zeal to drive high team performance Good problem solving and debugging skills Strong verbal written communication skills We are SiemensA collection of over 377 000 minds building the future one day at a time in over 200 countries We re dedicated to equality and we encourage applications that reflect the diversity of the communities we work in All employment decisions at Siemens are based on qualifications merit and business need Bring your curiosity and creativity and help us shape tomorrow We offer a comprehensive reward package which includes a competitive basic salary variable pay other benefits pension healthcare and actively support working from home We are an equal opportunity employer and value diversity at our company We do not discriminate based on race religion color national origin sex gender gender expression sexual orientation age marital status veteran status or disability status LI-EDA LI-Hybrid
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