Senior Soc Test bench Verification Engineer

Job Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

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SENIOR SILICON DESIGN ENGINEER

- THE ROLE (SOC Verification Engineer: SOC infra/tb/integration/formal):

- Work on SOC level integration activities, the person will be responsible for integration of IP, subsystem. Work in testbench team to close on initial bringup of SOC and cleaning up smoke and sanity cases.

- He will require co-ordination with IPs, SOC (Design, DFT & PD) teams. To take complete IP integration responsibility, including soc testbench bringup and the deployment verification.

- Person should be handson SOC testbench bringup, UVM and C understanding, DPI understanding, Integration of TB through automated process.

- He should be able to bringup formal testbench and setup.

THE PERSON:

- Engineer with strong self-driving ability.

- Need excellent communication skills (both written and oral)

- Strong problem-solving skills, go to person for Testbench, integration and formal.

- He should be handson on UVM and C. He should know all the phasing of UVM and Testbench

KEY RESPONSIBILITIES:

- SOC level integration activities and help in TB bringup at SOC. Understanding of Boot flow.

- IP deployment to complex SOCs and get the integration testing done.

- Testbench coding, Testcase coding, Debugging issues, regressions, UVM agent coding, checkers coding, scoreboard coding and Assertions coding.

- Formal setup bringup and TB bringup

- Automation of integration and testbench.

PREFERRED EXPERIENCE:

- Expertise in IP, Subsystem and SOC Verification with specialization in Integration, verification tools

- Strong hands-on experience in different SOC Verification activities, UVM, System Verilog, kv, X86, C++, HW/SW co-verification, Testbench bringup, DPI,Test plan review, Debug/triage, Coverage, Strong Problem Solving, Automation and Debugging Skills, Expert in scripting (phython, Java, C/C++).

- Comfortable with design/verification tools and flows like VCS, Verdi, SOC Connectivity, SV assertions, HW-SW co-simulations, UPF/CPF flows etc.

- Strong understanding of System integration, Make file flow, Verification Methodologies, Boot up sequence.

- JIRA based project management is a plus.

ACADEMIC CREDENTIALS:

- BE/B.Tech/ME/MTECH/MS or equivalent in ECE/EEE/CSE

- 5-8 years of strong DV experience Testbench, IP deployment/integration, formal, scripting and UVM.

#LI-SR4

Benefits offered are described: .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

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