Low Power Verification
3 weeks ago
**Job Details - Low Power Verification**:
**Job ID**:
- SPT Job No 17**Job Title**:
- Low Power Verification**Job Type**:
- Permanent**Job Location**:
- Bangalore**Total Experience**:
- 3 - 10 Years**Skills**:
- Rtl/2, Verification, Soc**Posted - **13/05/2023
**Job Description**:
Low Power Design Engineer - 3-10yrs
Power estimation,Performing synthesis,understanding synthesis PPA Reports and investigating Timing constraints and RTL changes to improve PPA
Low power intent verification using CPF,UPF and define low power intent thru UPF,based on power spec for block/SOC having multiple power domains.
Writing UPF Constraintsand verifying with Synopsys VCLP
Experience with RTL generation and integration using Arm Socrates,NIC-400,core sight SOC -600,PCK-600etc
Expertise in interconnect protocols like AXI, AHB and APB
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