Dft-design for Testability

6 months ago

Tirunelveli, India Jemysto Tech Full time

5-7 YearsProject in in 16nm or below, Mixed signal IC.
- Synopsys TestMAX experience
- Stuck-at ATPG
- Transition fault and path-delay ATPG
- Tester failure debug experience
- Excellent in scripting

**Nice-to-have**:

- ATPG flow development
- RTL DFT analysis
- PrimeTime DFT scripting for at-speed patterns
- SPF porting for analog-on-top design
- BIST pattern development using Synopsys tools"