Design and Verification
1 week ago
VLSI TRAINER JD
Experience : 0-4 years [can be Industrial Experience]
Education: B.tech/ ME/MTech
Type : Education / Training / Semiconductor
Functional Area: Training
Responsibilities:
Development and support High Speed and Low speed Interface Projects. Responsible for Debugging the source codes in Verilog, SV, and UVM. Responsible for Monitoring the trainee's progress. Will be a point of contact for trainees' queries on Technical concepts on design and Verification.
Should have knowledge on AMD64 Architecture.
Experience in DDR Protocol and any scripting like perl or python will be added advantage.
Salary - 2.5L - 4.0L
Location: Bangalore.
**Job Types**: Full-time, Part-time, Permanent, Temporary, Freelance, Volunteer
Contract length: 12 months
Pay: ₹250,000.00 - ₹450,000.00 per year
**Benefits**:
- Health insurance
- Leave encashment
- Paid time off
- Provident Fund
Schedule:
- Fixed shift
- Monday to Friday
- Morning shift
- Weekend availability
Supplemental pay types:
- Performance bonus
- Yearly bonus
**Education**:
- Bachelor's (preferred)
**Experience**:
- total work: 1 year (preferred)
- Design: 1 year (preferred)
License/Certification:
- Training experience (required)
Expected Start Date: 02/05/2024
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