Prin Engr, Digital
2 months ago
**Duties/Responsibilities**
- Propose, Architect, and Design RTL in Verilog for use in a Mixed Signal Integrated Circuit
- Contribute within a highly experienced team of engineers with extensive cross-functional skill sets
- Employ clocking controls, FSM design, low power techniques, and high-speed design concepts
- Participate in design, architecture, and verification reviews
- Cover digital backend design from synthesis, static timing and logic equivalent checking
- Creating documentation targeting design, verification, and test groups
- Assisting with new feature proposal, definition, documentation, and implementation
- Mentor and help train junior and New College Grad engineers
**Preferred Skills/Knowledge**
- Experience with architecting digital designs and writing device-level or sub-system specifications
- Experience in digital design implementation including logical synthesis and DFT insertion with high coverage
- Experience in static timing analysis and creation of place and route constraints
- Experience in formal verification, lint and CDC/RDC checking
- Experience in asynchronous clock crossings and synthesis implications of RTL
- Experience in implementing and verifying ECOs on RTL, synthesized, and post route netlists
- Fluent in Verilog RTL coding and ASIC design methodology is a must
- Competence in developing design constraints for synthesis, STA and P&R hand-off
- Experience with gate-level simulations, causes and implications of timing violations
- Experience in ATPG generation and ATE support is a plus
- Experience in DFT or physical design is a plus
- Experience with Verilog and/or SystemVerilog for digital design and verification is a plus
- Excellent oral and written communications skills
- 8+ years of direct experience in ASIC/IC design with deep knowledge of whole IC design flow
**Education**
Masters in Electrical Engineering, Computer Engineering, Computer Science, or equivalent with 8+ years of experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent with 10+ years of experience
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