Mts Layout Design
3 weeks ago
Overview:
**Responsibilities**:
- Owning and driving layout design of assigned macros with Cadence Virtuoso XL/VXL features.
- Responsible for scratch layout development and ECO fixes on an aggressive schedule.
- Expertise in layout verification checks LVS, DRC, Antenna, Density with Calibre is a must.
- Interact and collaborate with circuit designers, CAD across the globe to solve layout issues.
- Experience in fixing various reliability issues EMIR, ESD/Latchup.
- Strong debug capabilities with extraction, lvs/drc and other LV checks.
- Expertise in standard layout practices such as Layout matching, parasitic, noise & noise isolation, supply consideration, latch up, shielding, Well’s substrates and Isolation.
- Should have strong collaboration with Analog Designers across the globe to solve challenging problems.
Qualifications:
- Degree in Electrical/Electronic Engineering or equivalent with 6 to 10 years of relevant experience.
- Experience in layout design of Transmitter, receiver, PLL, Bandgap and voltage regulators, oscillators would be an added benefit.
- Should have layout experience in 40nm, 28nm, 22nm, to FINFET nodes 16nm, 12nm, 7nm.
- Strong fundamental knowledge in semiconductor device physics, cross-section, and construction.
- Sound knowledge of double patterning, device matching, signal shielding, layout parasitic, high speed signal integrity, and layout dependent effects.
- Having exposure to chip level floorplan, pad understanding, power grid design and EMIR fixes at chip level are preferred.
- Knowledge of skill/Perl/tcl scripting is plus.
- Good team player with self-motivation and excellent communication skills.
**About Rambus**
Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits.
Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services.
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