Asic Rtl- Fpga Design Architect
4 weeks ago
**Work Location **:Bangalore
**, Germany, USA**
**Relevant Expertise**: 7 - 12 Yrs
**Desired Profile**:
- Expertise in Logic design or micro-architecture or RTL coding for design and integration of complex multi clock domain Designs
- Experience in Verilog or System-Verilog with knowledge of AMBA, AXI, AHB, APB, Ethernet, USB, H264, H265, clocking or reset or debug architecture
- Experience in Multi Clock designs, Asynchronous interface, Constraint development & Timing Closure
- Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Experience in Low power design, Synthesis and timing concepts for ASIC
- Experience in creating pad ring and working with the chip level floorplan team is an added advantage
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