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Asic Verification Engineer
1 month ago
The ideal candidate will be responsible for verifying complex digital designs at the IP, subsystem, or So C level.
This role requires a strong understanding of verification methodologies, digital design concepts, and industry-standard protocols.
Key Responsibilities: Develop and execute detailed verification plans based on design specifications.
Build and maintain robust and reusable testbenches using System Verilog and UVM .
Perform functional, regression , and coverage-driven testing for digital IPs and So Cs.
Analyze and debug RTL failures using simulation tools and waveform viewers.
Collaborate with design, architecture, and firmware teams to identify and resolve issues.
Contribute to the development of verification IPs and methodology improvements.
Track and report verification metrics, coverage statistics, and bug status.
Required Skills & Qualifications: Bachelor's or Master's degree in Electronics , Electrical Engineering , or a related field.
Solid hands-on experience in System Verilog , UVM , and RTL simulation.
Proficiency in verifying standard interfaces such as AXI , AHB , APB , PCIe , or DDR .
Strong debugging skills and experience with tools such as VCS , Questa Sim , or Xcelium .
Familiarity with functional coverage , code coverage , and assertion-based verification .
Scripting knowledge in Python , Perl , or TCL for automation is an advantage.
Excellent communication and collaboration skills.
Preferred Qualifications: Experience with Formal Verification , Low Power Verification (UPF) , or Emulation is a plus.
Prior experience in Silicon bring-up or post-silicon validation is desirable.