Senior Design Engineer
4 weeks ago
Design and develop high speed interface PHY and its sub-block such as high speed data paths, analog calibration, training, IP initialization, low power control, test, loopback etc SKILLS required: Strong fundamental knowledge of digital design, Verilog and scripting languages Experience with micro-architecture and Asynchronous digital designs Working knowledge of Synthesis, DFT, STA, Lint & CDCWork closely with design teams to understand the requirements and constraints of the design.
Write and implement block level and top-level constraints for synthesis and STA.
Experience of performing STA preferably with both Tempus and Primetime STA and Timing closure using MMMC in both functional and DFT modes Experience on SDF generation and validation and support to functional verification team during GLS.
ETM /timing model generation and validation at IP level.
Working in partnership with So C teams to support the IP at So C level.
Experience in domain transfer designs, APB/JTAG, DFIExperience Required: 4+ Years Location - Bangalore Only
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Senior Design Verification Engineer
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Senior Design Verification Engineer
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Senior Design Verification Engineer
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