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AMS Verification

1 month ago

Delhi, India Texas Instruments Full time
Basic Qualifications:

- 1-2 years of experience in AMS design verification- to develop verliog/verilogA/verilogAMS models for signal and power management modules, to support Top level verification- experience in full chip DV will be an added advantage- to contribute to development of Full-Chip AMS -DV plan & own significant pieces of this verification.- and ability to drive best practices in the field of AMS-DV- to work independently, identify bugs and resolve them formally, with cross-functional teams- understanding of analog power IP’s that can help debug of Chip level AMS bugs- in usage of tools such as Cadence Virtuoso, Spectre &spice simulation, Incisive and AMS simulators. Utilize RTL and Gates+SDF including process variation in back-annotated timing simulations, including verifying chip-level timing between analog and digital circuits, parasitic resistance and capacitance, and using Assura parasitic extraction tools. Constrained-random stimulus and auto-checking verification environments, especially constrained-random analog stimulus.- candidate should work efficiently in a fast-paced product development environment, manage bug tracking and RTL code coverage, work with design and systems teams to close bugs as they arise; review the digital and analog design to provide guidance on Design for Verification architecture and features during chip development.

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