Senior Design Verification Engineer
2 weeks ago
etc using leading edge methodologies like
UVM
&
Formal DVArchitect the testbench and develop the verification environment
in UVM and Formal based verification approachesDefine testplan, tests and verification methodology for block / sub-system level verification. Work with design team in generating test-plans and closure of code and functional coverage. Integrate the block testbench at sub-system level UVM environment and verify integration. Interact with analog co-sim and firmware team in enabling toplevel chip verification aspectsPackage verification environment for Digital IP for seamless integration into verification flow at different stages of executionEvaluate 3rd party IPs on key qualitative aspects such as design quality, robustness of Design Verification (DV) practice, ease of DV environment integration and make recommendations. Establish evaluation flows for home-grown & 3rd party IPs for consistent benchmarking of DV evaluationBuild expertise on complex interfaces, peripherals & protocols such as DDR, Ethernet, eMMC/ SD, MIPI, Display Port, HDMI, PCIe, high speed D2DSupport post-silicon verification activities of the products working with design, product evaluation and applications engineering teamPosition Requirements:Minimum B.E./ B.Tech degree in Electrical/Electronics/Computer science2 - 6 years of experience in design verification with UVM and constrained random, coverage-based verification approachesStrong understanding of DV concepts with an eye on developing scalable DV environment architecture that realizes first pass DV successExperience with translating Design Verification (DV) requirements such as test plans into a robust DV environment and generate coverage metrics for demonstrating DV convergenceAdaptability to learn end application/systems and map into smart verification test plansExcellent debugging and analytical skillsGood interpersonal, teamwork and communication skills to logically & effectively drive discussions with teams spread geographicallyKnowledge of Assertion based formal verificationUnderstanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols is a strong plusKnowledge of Processor/SoC architecture and/or DSP fundamentals is a strong plusExperience with ASIC/ SoC product DV & productization is very desirableJob Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days
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1 month ago
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Sr Design Verification Engineering Manager
1 month ago
Bengaluru, India Cadence Design Systems Full timeJob Description:Roles & Responsibilities:Exp- 12 - 16 yrs The role requires the management of a SerDes DV group focusing on MDV verification including: Constrained Random Functional Verification, Formal Property Verification, project DV status and execution, and mentorship of junior engineers.The role requires the ability to work with the existing functional...
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Sr Design Verification Engineering Manager
1 month ago
Bengaluru, India Cadence Design Systems Full timeJob Description: Roles & Responsibilities: Exp- 12 - 16 yrs The role requires the management of a SerDes DV group focusing on MDV verification including: Constrained Random Functional Verification, Formal Property Verification, project DV status and execution, and mentorship of junior engineers. The role requires the ability to work with the existing...
