Lead Engineer

4 weeks ago

noida, India NXP Semiconductors Full time

Job Opportunity: Seeking highly motivated, energetic, team-oriented Individual Contributorwilling to go deeper into logic design and take the challenge ofdeveloping Complex state of the art IPs using the latest advanced Design flow methodologies and efficient techniques.

The personwill be workingclosely with experienced and motivated team of Systems, SoC Design functions to address the design/architectural challenges in the context of the complex IP, Subsystem and overall System level designs, towards providing a complete solution with end to end design flow from High level Specifications to actual design Implementation. 

Key Responsibilities

Design and Develop complex IP and Subsystems across a range of protocolsrequired for Automotive Self Driving Vehicles (ADAS) both Vision and Radar, In-Vehicle networks, Gateway Systems, Fail Safe Subsystems (ASIL-D) etc.

Lead or be part of IP / Subsystem team from Concept till IP Design and Development achieving final design performance in integrated system within aggressive, market driven schedules. 

Ensure quality adherence during all stages of the IP development cycle and carry out a thorough implementation of existing processes,or build methodologyto ensure ‘Zero Defect’ designs.

Ability to work well as part of a team of global and local experts to influence and build technological innovations. 


Key Skills

Self starter with 3-7 years of experienceto Design and develop complex IPdesign /Sub-system with minimal or no supervision.

Custom Processor Designs with key DSP functionslike those needed for Vision and Radar processing, Processor Design, Cache Design

Experience in High Speed Serial protocols and associated high speed challenges on controller and PHY for PCIe, Ethernet & MIPI CSI2. 

Understanding of key External Memory interface protocols including DDR4 / LPDDR4, QuadSPI Flash interfaces.

Experience in microcontroller architecture, bus protocols like AHB/AMBA,AXI.

Experience in automotive protocols like LIN,CAN,Flexray – would be advantageous.

Hands on knowledge of HDLs(Verilog/VHDL) & Scripting languages (Perl, Tcl), C/C++ for hardware modeling. 

Understanding of end to end IP development flow including complex CDC, RDC constructs, IP Synthesis, DFT ATPG coverage. 

Understanding and having worked on Testbench and Testplan development and on Pre-Silicon validation of IP on FPGA / Emulation board would be a significant added advantage as well.

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