Asic rtl engineer
17 hours ago
Senior ASIC/So C RTL Engineer/Lead (IP RTL design targeted for SOC, Static checks, some basic protocols) Exp - 4 - 20 Location : Bengaluru, Hyderabad, Pune, Noida, Kochi Expertise in So C subsystem/IP design Expertise in IP design, Subsystem/Cluster and So C level integration using Verilog/System Verilog In depth knowledge on RTL quality checks (Lint, CDC) Knowledge of synthesis and low power is a plus Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB) Good understanding of timing concepts Knowledge of one or more of the interface protocols - PCIe -DDR -Ethernet - I2 C, UART, SPI Expertise in setting up and using tools like -Spyglass Lint/CDC -Synopsys DC -Verdi/Xcellium Understanding of scripting languages like Make flow, Perl ,shell, python etc Understanding of processor architecture and/or ARM debug architecture is a plus Able to help and debug issues for multiple subsystems Able to create/review design documents for multiple subsystems Able to support physical design, verification, DFT and SW teams on design queries and reviews About Us: Wipro Limited (NYSE: WIT, BSE: , NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With nearly 245,000 employees and business partners across 65 countries, we deliver on the promise of helping our clients, colleagues, and communities thrive in an ever-changing world. Wipro is an Equal Employment Opportunity employer and makes all employment and employment-related decisions without regard to a person's race, sex, national origin, ancestry, disability, sexual orientation, or any other status protected by applicable law.
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ASIC RTL Engineer 4+ years Bangalore
5 days ago
Bangalore, India ACL Digital Full timeRTL Design: Design and implement RTL code for ASICs in Verilog or SystemVerilog. Create high-quality, reusable, and maintainable RTL code for complex digital systems. Architecture Design: Work closely with architects to understand the high-level design specifications and translate them into efficient RTL code. Participate in defining micro-architecture for...
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Asic rtl design engineer
17 hours ago
Bangalore, India 7hillsTS Full timeKey skills with hand on: ASIC, RTL Design, VLSI-SOC , AMBA, Lint, CDC, Synopsys Lint CDC/Verdi Xcellium/Synopsys DC. Experience: 5 - 25 years Work Location: Trivandrum, Bangalore, Hyderabad, Chennai, Pune Education: Engineering (excluding Mechanical/Civil) Detailed JD: IP RTL design targeted for SOC, Static checks, some basic protocols Expertise in...
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Rtl engineer/ rtl lead and above
17 hours ago
Bangalore, India Tessolve Full timeOpportunity With Tessolve Semiconductor- Bangalore Hi All, we are hiring RTL design engineer and design verification engineer for Bangalore location. Exp: 5+ yr exp Skills: RTL ASIC, CDC, Lint, Synthesis, Spyglass We are hiring for RTL ASIC engineer 7f work experience in ASIC/IP Design. Experience in Logic design / RTL design Experience is IP design...
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ASIC RTL Engineer
6 days ago
Bangalore, India Wipro Full timeSenior ASIC/SoC RTL Engineer/Lead (IP RTL design targeted for SOC, Static checks, some basic protocols) Exp - 4 - 20 Location :Bengaluru, Hyderabad, Pune, Noida, Kochi Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog In depth knowledge on RTL quality checks...
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ASIC RTL Engineer
5 days ago
Bangalore, India Wipro Full timeSenior ASIC/SoC RTL Engineer/Lead (IP RTL design targeted for SOC, Static checks, some basic protocols) Exp - 4 - 20 Location :Bengaluru, Hyderabad, Pune, Noida, Kochi Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog In depth knowledge on RTL quality checks...
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ASIC RTL Engineer
5 days ago
bangalore, India Wipro Full timeSenior ASIC/SoC RTL Engineer/Lead (IP RTL design targeted for SOC, Static checks, some basic protocols)Exp - 4 - 20Location :Bengaluru, Hyderabad, Pune, Noida, KochiExpertise in SoC subsystem/IP designExpertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System VerilogIn depth knowledge on RTL quality checks (Lint, CDC)Knowledge...
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ASIC RTL Engineer 4+ years Bangalore
6 days ago
Bangalore Urban, India ACL Digital Full timeRTL Design: Design and implement RTL code for ASICs in Verilog or SystemVerilog. Create high-quality, reusable, and maintainable RTL code for complex digital systems.Architecture Design: Work closely with architects to understand the high-level design specifications and translate them into efficient RTL code. Participate in defining micro-architecture for...
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Asic design engineer
17 hours ago
Bangalore, India ACL Digital Full timeASIC Design Engineer We are seeking a skilled ASIC Design Engineer with a solid background in digital design, RTL coding, and ASIC development. The ideal candidate will have extensive experience in designing, developing, and optimizing high-performance ASICs, with a strong focus on System Verilog or VHDL. This role will involve taking designs from concept...
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ASIC RTL Design Engineer
6 days ago
Bangalore, India 7hillsTS Full timeKey skills with hand on: ASIC,RTL Design, VLSI-SOC ,AMBA, Lint, CDC, Synopsys LintCDC/VerdiXcellium/Synopsys DC. Experience: 5 - 25 years Work Location: Trivandrum, Bangalore, Hyderabad, Chennai, Pune Education: Engineering (excluding Mechanical/Civil) Detailed JD: IP RTL design targeted for SOC, Static checks, some basic protocols ...
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ASIC RTL Design Engineer
5 days ago
bangalore, India 7hillsTS Full timeKey skills with hand on: ASIC,RTL Design, VLSI-SOC ,AMBA, Lint, CDC, Synopsys LintCDC/VerdiXcellium/Synopsys DC.Experience: 5 - 25 yearsWork Location: Trivandrum, Bangalore, Hyderabad, Chennai, PuneEducation: Engineering (excluding Mechanical/Civil)Detailed JD:IP RTL design targeted for SOC, Static checks, some basic protocolsExpertise in SoC subsystem/IP...
