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Senior Physical Design Engineer
2 months ago
you will be responsible for the high-performance CPU implementation, and timing closure. You'll be a key contributor to our innovative technology solutions, ensuring that designs meet timing, power, and area budgets. As a part of our dynamic team, you will also play a crucial role in implementing engineering change orders (ECOs) to address functional bugs and timing violations. We value team players with strong problem-solving and communication skills who are ready to make a significant impact in shaping the future of technology.
Your Role and Responsibilities :•
Perform Sub system level floor planning, placement, and routing for high-performance CPU design.•
Collaborate with cross-functional teams to achieve design goals.•
Close the design to meet timing, power, and area requirements.•
Implement engineering change orders (ECOs) to rectify functional bugs and timing issues.•
Ensure the quality and efficiency of the RTL to GDS2 implementation process.Required Professional and Technical Expertise :•
8-12 years of industry experience•
Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, routing , post route closure.•
Should be knowledgeable in physical verification ( LVS,DRC.. etc) ,Noise analysis, Power analysis and electro migration .•
Good knowledge and hands on experience in static timing analysis (closing timing at chip level)•
good understanding of timing constraints .•
Should have experience in handling asynchronous timing, multiple corner timing closure.Preferred Professional and Technical Expertise :•
Automation skills in PERL ,SKILL and/or TCL
Contact:UdayMulya Technologies"Mining The Knowledge Community"
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