Principal Engineer ASIC DV

1 week ago

hyderabad, India Mulya Technologies Full time

Principle Engineer ASIC DV

Top10 Semiconductor Organization in the World

Hyderabad



Position Description:

  • Verify the RTL code for the high speed SerDes IP and its related digital blocks along with compliance with the standard body protocols such as MIPI, PCIe etc.
  • Responsible for overall IP and sub-system verification from test plan creation, UVM development to signoff.
  • Ensure first pass product through multi-dimensional verification coverage including mixed mode verification.
  • Pair with Architects, Digital, SoC DV and FW engineers across the geographies for flawless execution and first-time silicon pass.
  • Leading, mentoring and coaching junior team members
  • Work closely with Digital and Analog designers
  • Equal opportunity position with excellent pay package

SKILLS required:

  • Experience in design verification of complex high speed SERDES PHYs such as MIPI, PCIe etc
  • Proven track record of building testplan, UVM environment and testbenches
  • Experience with RTL debugging, score boarding and code coverage analysis
  • Sound knowledge of Verilog and System Verilog languages
  • Exposure to modelling and validating complex analog circuits in Verilog and Verilog-A
  • Experience of complex mixed signal design verification using state of the art flows and tools
  • The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams.
  • Team leadership experience, including planning and managing tasks is desirable
  • M.S./M.Tech, BS/BE (Electronics)
  • Experience Required: 12+ Years




Contact:

Uday

Mulya Technologies

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