PD/ STA engineer

3+ years experience in STA/SynthesisHand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis.Hands-on the DMSA flow to fix pre and post STA timing.Knowledge on the Timing closure on Sub system level & Block level and Chip...

3+ years experience in STA/SynthesisHand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis.Hands-on the DMSA flow to fix pre and post STA timing.Knowledge on the Timing closure on Sub system level & Block level and Chip...

NVIDIA is looking for a best-in-class ASIC STA Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency for today's AI platforms! Come and take a part in designing our groundbreaking large scale and innovating chips, enjoy...

About the Role:We are seeking an experienced and dynamic Physical Design (PD) Lead to join our team. In this role, you will leverage your extensive expertise in physical design tools and methodologies to lead high-impact PD programs and guide large teams through the entire ASIC design flow. You will be responsible for leading end-to-end projects for one of...

Hi Folks,We are hiring for STA EngineerExp-3-8 yearsLocation- Bangalore/ Kochi/ Vizag/ AhmedabadJDDeep understating and experience of STA tool Tempus/PrimeTime /Tweaker/ DMSA(PTECO) .Knowledge of timing corners/modes, process variations and signal integrity related issues are required.Experience in timing closure of high frequency blocks & subsystems (Ghz...

Looking for STA Engineer.Exp.-3+yrs.Job Location- Bangalore.Netlist and constraint sign in checks and validation.Prime time constraint development at full chip level and clean up.Multimode multi corner timing knowledge and timing closure at sub HM/block/top level.Top level timing closure with sign off STA in MMMC with Xtalk and OCV. Top level ECO...

Looking for STA Engineer. Exp.-3+yrs. Job Location- Bangalore. Netlist and constraint sign in checks and validation. Prime time constraint development at full chip level and clean up. Multimode multi corner timing knowledge and timing closure at sub HM/block/top level. Top level timing closure with sign off STA in MMMC with Xtalk and OCV. Top level ECO...

Hi All,Greetings from #L&T Technology Services!!Role: Synthesis/STA EngineerExperience: 3+ YearsNP: Immediate to 30Days#Location: BangaloreJob Description:Candidate with 3+ years exp in Synthesis/STA roleExperience in handling complex data path-oriented multi-million gate synthesisWorking Knowledge of Physical synthesis using tools like Genus, Fusion...

Hi All, Greetings from #L&T Technology Services!! Role : Synthesis /STA Engineer Experience : 3+ Years NP : Immediate to 30Days #Location : Bangalore Job Description: Candidate with 3+ years exp in Synthesis/STA role Experience in handling complex data path-oriented multi-million gate synthesis Working Knowledge of Physical synthesis using tools like Genus,...

Staff - ASIC STA EngineerTop 10 Semiconductor Organization in the worldLocation: Bangalore Staff - ASIC STA EngineerPosition DescriptionThe position is part of a Mix-Signal ASIC digital team. The group owns various high-speed IPs (like ONFI & DDR PHY, SerDes) and IO buffer Chips from spec to post silicon characterization.Responsible for front end...

ACL Digital is hiring for PD and STA Engineers for Bangalore and Location.3+years of experience in Physical Design.Must have exp into floorplanning, STA blocks (2 blocks each) from synthesis, PnR, Timing and PV closure.Notice period Immediate to 30 days

Job Description:• Deep understating and experience of STA tool PrimeTime /Tweaker/ DMSA(PTECO) .• Knowledge of timing corners/modes, process variations and signal integrity related issues are required.• Experience in timing closure of high frequency blocks & subsystems (Ghz range )• Experience in working full-chip STA closure, defining mode...

ACL Digital is hiring for PD and STA Engineers for Bangalore and Location.3+years of experience in Physical Design.Must have exp into floorplanning, STA blocks (2 blocks each) from synthesis, PnR, Timing and PV closure.Notice period- Immediate to 30 days

We are looking for an STA Engineer in Bangalore for the following role and with the given background/skill sets. Does this sound like a good role for you?.Senior STA/Synthesis Engineer (Timing Constraint Manager product)Location: BangaloreExperience: 4yrs to 8yrsBachelor/Master in EE/CS with 4 years of relevant experienceProficiency with STA, and...

Job Description: Deep understating and experience of STA tool PrimeTime /Tweaker/ DMSA(PTECO) . Knowledge of timing corners/modes, process variations and signal integrity related issues are required. Experience in timing closure of high frequency blocks & subsystems (Ghz range ) Experience in working full-chip STA closure, defining mode requirements and...

Job Description:- Deep understating and experience of STA tool PrimeTime /Tweaker/ DMSA(PTECO) .- Knowledge of timing corners/modes, process variations and signal integrity related issues are required.- Experience in timing closure of high frequency blocks & subsystems (Ghz range )- Experience in working full-chip STA closure, defining mode requirements...

JD:Should have hands on experience with Static timing analysis and timing constraints generation as per designer input.Experience with tempus tool, SDC, primetime.Working knowledge of TCL/Python is an add-on.Experience is 4+yrs (no junior profile please)Notice period: Immediate to 30 Days.

JD For STA Engineer-5+ years’ experience- Good knowledge of timing closure knowledge for high frequency timing, congestion, and area sensitive designs.- Can work closely with FE team for constraints development and constraints cleanup.- Work with partitions/block owner to give timing ECO for timing closure.- Knowledge of advanced timing closure...

JD For STA Engineer-5+ years’ experience-Good knowledge of timing closure knowledge for high frequency timing, congestion, and area sensitive designs.-Can work closely with FE team for constraints development and constraints cleanup.-Work with partitions/block owner to give timing ECO for timing closure.-Knowledge of advanced timing closure techniques and...

Hi Folks,We are hiring for STA EngineerExp -5 - 7 YearsLocation- Bangalore/ Kochi / Vizag / Ahmedabad JDUnderstand the timing concepts- Full chip Timing (FCT) timing closure experience- Constraints- false_path/multi_cycle_paths- IO timing- Timing ECO generation- clock balancing for timing closure- Annotation checking analysis- STA quality checks-...