IP RTL Design

RTL IP/Logic Design Engineers / Design Architect LeadsThis position is for IP Design Engineer Lead/manager role at Samsung Semiconductor India Bangalore, where you will be involved in RTL design, synthesis and verification of various complex IP modules of SSD/Flash storage products. You will be associated in the design development life cycle to support spec...

6 to 15 years of work experience in VLSI RTL IP or Subsystem design. Based on prior skill and desire to learn, the new hire will contribute in either SoC Clock, SoC Power IP/Subsystem, BUS/Subsystem, Peripherial/CPU/GPU Subsystem or other Mobile SoC Subsystem.In depth understand of Digital design principles. AMBA SoC BUS protocols specifically APB, AXI and...

6 to 15 years of work experience in VLSI RTL IP or Subsystem design. Based on prior skill and desire to learn, the new hire will contribute in either SoC Clock, SoC Power IP/Subsystem, BUS/Subsystem, Peripherial/CPU/GPU Subsystem or other Mobile SoC Subsystem. 1. In depth understand of Digital design principles. AMBA SoC BUS protocols specifically APB, AXI...

6 to 15 years of work experience in VLSI RTL IP or Subsystem design.Based on prior skill and desire to learn, the new hire will contribute in either So C Clock, So C Power IP/Subsystem, BUS/Subsystem, Peripherial/CPU/GPU Subsystem or other Mobile So C Subsystem.1.In depth understand of Digital design principles.AMBA So C BUS protocols specifically APB, AXI...

RTL IP/Logic Design Engineers / Design Architect LeadsThis position is for IP Design Engineer Lead/manager role at Samsung Semiconductor India Bangalore, where you will be involved in RTL design, synthesis and verification of various complex IP modules of SSD/Flash storage products. You will be associated in the design development life cycle to support spec...

RTL IP/Logic Design Engineers / Design Architect LeadsThis position is for IP Design Engineer Lead/manager role at Samsung Semiconductor India Bangalore, where you will be involved in RTL design, synthesis and verification of various complex IP modules of SSD/Flash storage products. You will be associated in the design development life cycle to support spec...

RTL IP/Logic Design Engineers / Design Architect Leads This position is for IP Design Engineer Lead/manager role at Samsung Semiconductor India Bangalore, where you will be involved in RTL design, synthesis and verification of various complex IP modules of SSD/Flash storage products. You will be associated in the design development life cycle to support...

RTL IP/Logic Design Engineers / Design Architect LeadsThis position is for IP Design Engineer Lead/manager role at Samsung Semiconductor India Bangalore, where you will be involved in RTL design, synthesis and verification of various complex IP modules of SSD/Flash storage products. You will be associated in the design development life cycle to support spec...

RTL IP/Logic Design Engineers / Design Architect LeadsThis position is for IP Design Engineer Lead/manager role at Samsung Semiconductor India Bangalore, where you will be involved in RTL design, synthesis and verification of various complex IP modules of SSD/Flash storage products. You will be associated in the design development life cycle to support spec...

Position SummarySecure an optimal digital IP and circuit by understanding required functions to be developed and designing and verifying them in line with the required goals.Role and ResponsibilitiesJob Profile - RTL Micro-architecture Design Engineer (SOC Integration)5 to 15 years of work experience in VLSI RTL IP or Subsystem design. Based on prior skill...

6 to 15 years of work experience in VLSI RTL IP or Subsystem design. Based on prior skill and desire to learn, the new hire will contribute in either SoC Clock, SoC Power IP/Subsystem, BUS/Subsystem, Peripherial/CPU/GPU Subsystem or other Mobile SoC Subsystem. 1. In depth understand of Digital design principles. AMBA SoC BUS protocols specifically APB, AXI...

6 to 15 years of work experience in VLSI RTL IP or Subsystem design. Based on prior skill and desire to learn, the new hire will contribute in either SoC Clock, SoC Power IP/Subsystem, BUS/Subsystem, Peripherial/CPU/GPU Subsystem or other Mobile SoC Subsystem. 1. In depth understand of Digital design principles. AMBA SoC BUS protocols specifically APB, AXI...

6 to 15 years of work experience in VLSI RTL IP or Subsystem design. Based on prior skill and desire to learn, the new hire will contribute in either SoC Clock, SoC Power IP/Subsystem, BUS/Subsystem, Peripherial/CPU/GPU Subsystem or other Mobile SoC Subsystem. 1. In depth understand of Digital design principles. AMBA SoC BUS protocols specifically APB, AXI...

6 to 15 years of work experience in VLSI RTL IP or Subsystem design. Based on prior skill and desire to learn, the new hire will contribute in either SoC Clock, SoC Power IP/Subsystem, BUS/Subsystem, Peripherial/CPU/GPU Subsystem or other Mobile SoC Subsystem. 1. In depth understand of Digital design principles. AMBA SoC BUS protocols specifically APB, AXI...

* **RTL Design - Lead Engineer** **Relevant Experience**:4 to 12 years - Strong knowledge in IP/SOC design methodologies. - Sound knowledge of RTL design with Verilog/system Verilog and front-end design tools & flows - Good experience in Synthesis - Good communication skills to work in a cross functional international team digital and software design...

Design & synthesize for a complex SerDes IPs in various technology nodes (> 100G rates)Work with Analog design teams to co-develop algorithms, feedback design loops as well as high speed critical digital circuitsGood understanding of working with signal processing IPs in terms of knowing calibrations, PLLs, dividers, FIFO design and reset...

Be part of the Cadence High-Speed SerDes PHY IP Front end Design team responsible for Defining microarchitecture of digital blocks involving microcontroller-based designs to meet specifications, optimized for performance metrics of timing, area, and power.-Lead and also hands-on end-to-end ASIC design including RTL implementation and design processes of...

Be part of the Cadence High-Speed SerDes PHY IP Front end Design team responsible for --Defining microarchitecture of digital blocks involving microcontroller-based designs to meet specifications, optimized for performance metrics of timing, area, and power.-Lead and also hands-on end-to-end ASIC design including RTL implementation and design processes of...

Job Description: B.tech or M.tech with 5+ years of experience on FE tools like Spyglass cdc and spyglass lint. Should have sound knowledge on synthesis and low power. Should have good knowledge on RTL coding and integration with excellent debug skills. Knowledge on git and CC framework will be better.Role involves running FE tools on DSP designs and...

Job Description :Our client provides end to end semiconductor design services covering digital, analog, system design & embedded software. They are poised to be the fastest growing semiconductor services company.They are looking for RTL Designer/Coding to be based at Bangalore / Noida with the following : 4 to 11 years relevant industry experience in the...