Logic Design lead cache
2 days ago
- #ISAIS 8 to 20 years of relevant experience
- At least 1 generation of processor L2 cache or LLC design delivery leadership.- Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP.- Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations.- Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory.- Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.
Contact
Uday
Mulya Technologies
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