Senior Firmware Manager

1 week ago

Hyderabad, India Mulya Technologies Full time
Senior Manager FWTop10 Semiconductor Organization in the worldHyderabad

As a NVEG DE Design Engineer at ., you will be responsible for designing and analyzing digital circuits used in the development of memory products. This includes simulating, optimizing, and floor planning NAND circuits. In this position you will work and support the efforts of groups inside of NVE-DE organization such as Project Teams as well as other Functional Teams (Analog, Core, Datapath, etc) as well as the teams outside of NVE-DE organization such as Product Engineering, Device, System, Test, Probe, Process Integration, Assembly and Marketing to proactively design products to optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction. You will also be responsible for designing the algorithms in the on-chip controller, for the non-volatile memory products, also design validation at block, subsystem, and fullchip level.

Responsibilities and Tasks

Contribute to the Development of New Memory Products by Assisting with Algorithm Design and Firmware Development for the Internal NAND Operations, the Overall Logic Design, and Optimization of Memory Circuits.• Responsible for meeting the performance/area/power targets• Ability to interpret device and system specifications to produce required functionality• Participate in new circuit conception and design as needed• Define and create design architecture spec documents for the new features• Assist in design and development of schematics and/or RTL blocks

Manage and Develop Projects and Team (Leads)• Plan and organize projects and resource requirements, including planning, and scheduling activities and tasks, and management of designers wrt all new requests• Serve as main point of contact for communication for the algorithm design and development for the NAND product• Track progress, monitor when items are completed and what still needs to be done• Prepare project status reports for upper management• Plan and hold code reviews to discuss progress and decisions made about project• Mentor new hires and supervise progress• Create training programs for ramping up of team members

Manage Verification Processes• Perform RTL and synthesized netlist (gate level) verification at fullchip level• Facilitate netlist bring up to achieve basic functionality• Responsible for design simulation including post layout• Create verification plan for new and existing features and check expected behavior in Verilog• Collaborate with Product Engineering wrt validation plan and review Silicon result• Assist in silicon design validation, reticle experiments, qual and tape-out revisions as needed

Maintain Technical Expertise and Provide training• Define best known design and verification practices and communicate to the entire department• Prepare detailed documentation as required• Participate in recruiting, and interviewing of new candidates• Create new hire ramp up plans• Engage in continuing education and competitor analysis

Contribute to Cross Group Communication to Work Towards Standardization and Group Success• Work with Device, System, Probe, Test, CAD, Field Application Engineers, and Product Engineering groups to ensure proper manufacturability of product• Proactively solicit input from various groups (i.e. Standard cell development; simulation, voltage)

Contact:UdayMulya

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