Senior design verification engineer

4 weeks ago

Bangalore, India ACL Digital Full time

Senior Design verification Engineer Mandatory Skill : PCIE Location : Bangalore Experience : 5 years Design Verification Engineer responsible for ensuring functional correctness of ASIC/So C designs. Key Task: Develop and execute verification plans for complex digital designs. Methodology: Use UVM/System Verilog to create testbenches, write test cases, and debug failures. Coverage: Achieve functional and code coverage targets through constrained random and directed testing. Collaboration: Work with RTL designers to identify and resolve design bugs. Tools: Leverage industry-standard tools (VCS, Questa, Verdi) for simulation and debug. Protocols: Verify IP/So C-level designs for common protocols (AXI, APB, PCIe, DDR, etc.). Automation: Develop scripts (Python/Perl/TCL) to improve verification efficiency. Documentation: Maintain verification reports and review results with stakeholders. Compliance: Ensure adherence to project timelines and quality standards. Interested,please drop your updated CV to

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