Senior Design Verification Engineer

2 weeks ago

Bengaluru, India Proxelera Full time

Job Description:- 5+ Years of relevant experience in Design Verification.- Own UVM-based constrained-random verification for complex SoC/IP subsystems.- Develop testbenches, sequences, scoreboards, and checkers; close coverage (FC/CC/SC).- Must have SystemVerilog/UVM, assertions (SVA), functional coverage, and regressions.- Experience with bus protocols (AXI/AHB/APB/PCIe), cache/Coherency, and interrupts.- Debug with waveforms, CDC/RDC awareness, lint, and formal/property checks.- Tools: VCS/Questa/Xcelium, Verdi/DVE, Jenkins/CI, code reviews.- Strong scripting (Python/Perl/TCL), Make/CMake, version control (Git).- Work with architects/design/DFT/PD for spec clarification and sign-off.Mandatory Skills to be checked in CV- SystemVerilog / UVM- Assertions (SVA) / Functional Coverage- Protocols (AXI / AHB / APB / PCIe)- VCS / Questa / Xcelium + Python/TCL scripting

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