Dft- sr. lead
5 days ago
Design for Testability (DFT) Engineer (Senior Level - 10+ years’ experience) Job Summary: We are seeking a highly accomplished Design for Testability (DFT) Engineer to join our elite team and lead the DFT efforts for our most critical ASIC and So C projects. This senior-level position demands a mastery of DFT methodologies and the ability to drive the implementation of robust test strategies. You will play a pivotal role in ensuring the manufacturability and high-quality testing of our next-generation integrated circuits. Responsibilities: Lead and define the overall DFT strategy for assigned projects, considering manufacturability, test coverage, and cost optimization Collaborate with design and verification teams throughout the design flow to seamlessly integrate DFT techniques Develop and implement advanced DFT methodologies (scan insertion, ATPG, Boundary Scan, Design for X) to achieve exceptional test coverage and fault detection rates Champion best practices for DFT and actively participate in design reviews, providing expert guidance on DFT feasibility and optimization Lead and mentor junior DFT engineers, fostering a culture of excellence and knowledge sharing within the team Analyze test results, identify potential design issues, and recommend corrective actions to ensure high test quality Stay at the forefront of the DFT landscape by actively researching and adopting emerging tools and methodologies Manage and maintain DFT libraries and internal DFT standards Contribute to the continuous improvement of the DFT flow within the team Qualifications: Master's degree in Electrical Engineering, Computer Engineering, or a related field (highly preferred) Minimum of 10+ years of experience in Design for Testability (DFT) for complex ASICs and So Cs Proven track record of successfully leading and implementing DFT strategies for high-volume production In-depth knowledge of advanced DFT concepts (scan insertion, ATPG, Boundary Scan, Design for Reliability, Design for Power, etc.) Expertise in industry-standard DFT tools (Synopsys DFT Compiler, Tetra MAX, etc.) and scripting languages (Perl, TCL) for automation Strong understanding of digital design principles (combinational logic, sequential logic) and manufacturing test processes Excellent analytical and problem-solving skills with a focus on achieving optimal test quality and cost-effectiveness Effective leadership, communication, collaboration, and teamwork skills Benefits: Competitive salary and benefits package commensurate with experience and expertise Opportunity to lead and influence the DFT strategy for cutting-edge technologies Dynamic and challenging work environment with opportunities for professional growth and leadership development Recognition and rewards for outstanding contributions
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DFT- Sr. Lead
2 days ago
bangalore, India HCLTech Full timeDesign for Testability (DFT) Engineer (Senior Level - 10+ years’ experience) Job Summary: We are seeking a highly accomplished Design for Testability (DFT) Engineer to join our elite team and lead the DFT efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of DFT methodologies and the ability to drive the...
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DFT- Sr. Lead
5 days ago
bangalore, India HCLTech Full timeDesign for Testability (DFT) Engineer (Senior Level - 10+ years’ experience)Job Summary:We are seeking a highly accomplished Design for Testability (DFT) Engineer to join our elite team and lead the DFT efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of DFT methodologies and the ability to drive the...
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DFT Lead
3 weeks ago
Bangalore, India LeadSoc Technologies Pvt Ltd Full timeLead Soc is hiring DFT Leaders! Hands on experience working in DFT with scan insertion. Good communication and analytical skills and Team handling. Experience: 9 years to 20 years Location: Bangalore Please share your profile to jhansi.bv@leadsoc.com for further discussion
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Lead DFT Engineer
1 day ago
bangalore, India ACL Digital Full timeJob Title: Lead DFT EngineerExperience: 7+ Years Location: Bangalore Employment Type: Full-time Industry: Semiconductors / ASIC / SoC DesignJob Summary:We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with...
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Lead DFT Engineer
2 days ago
bangalore, India Tech Mahindra Full timeOpen position:- Lead DFT Engineer Experience: - 7+ years Location:- Bangalore NP: - Immediate to 15 days JD: - 1. Experience with DFT tools such as Synopsys DFT Compiler, Test Kompress and Xelium. 2. Minimum 7+ years of experience in DFT engineering, with a focus on Scan Insertion and ATPG, ICL, SSN 3. Strong knowledge of DFT techniques such as Scan Chains,...
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DFT Lead
4 days ago
bangalore, India Tech Mahindra Full timeHi Tech Mahindra hiring DFT Engineers for Bangalore location. Exp: 9-14yrs Location: Bangalore NP: 0-45days JD: 1. Experience with DFT tools such as Synopsys DFT Compiler, TestKompress and Xelium 2. 7+ years of experience in DFT engineering, with a focus on Scan Insertion and ATPG, ICL, SSN 3. Strong knowledge of DFT techniques such as Scan Chains, ATPG,...
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Lead DFT Engineer
1 week ago
bangalore, India ACL Digital Full timeJob Title: Lead DFT Engineer Experience: 7+ Years Location: Bangalore Employment Type: Full-time Industry: Semiconductors / ASIC / SoC Design Job Summary: We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers,...
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DFT Lead Engineer
2 days ago
Bangalore, India ACL Digital Full timeDFT Lead : Work Location - Bangalore Experience - 7+ Years Desired Skills and Experience – · 7+ years of experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. · DFT logic integration and verification. · Experience in debugging low coverage and DRC fixes · Gate Level ATPG simulation with and without timing. · Pattern...
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DFT Engineer
1 day ago
bangalore, India ACL Digital Full timeDFT - Senior/ Lead EngineerJob DescriptionScan insertion.SCAN DRC/ Coverage debug.ATPG Pattern generation.Gate level simulations ( Zero delay/Timing Delay simulations).Worked on JTAG/P1500 protocols.Perl/ Tcl scripting.Timing/ Formal verification/ PD flow knowledge is plus.Location: Bangalore
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Dft lead engineer
3 weeks ago
Bangalore, India ACL Digital Full timeDFT Lead : Work Location - Bangalore Experience - 7+ Years Desired Skills and Experience –· 7+ years of experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. · DFT logic integration and verification. · Experience in debugging low coverage and DRC fixes · Gate Level ATPG simulation with and without timing. · Pattern...
