Physical Design Engineer

2 weeks ago


Bangalore City, India Wafer Space - An ACL Digital Company Full time

Experience : 4 to 10 yearsLocation : BangaloreNotice Period : Immediate to 30 daysJob Description:● Deep understanding of the concepts related to synthesis, place & route, CTS, timingconvergence, IR/EM checks and signoff DRC/LVS closure.● Responsible for independent planning and execution of all aspects of physical designincluding floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction,Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM.● Must have participated in all stages of the design (floor planning, placement, CTS, routing,physical verification, IREM).● Well versed with the timing closure (STA), timing closure methodologies.● Good Understanding of DRC, LVS,ERC and PERC rule files for lower tech node layoutverification.● Experience in lower tech nodes (< 7nm).● Good automation skills in PERL, TCL and EDA tool-specific scripting.● Able to take complete ownership for Block/sub-system for complete execution cycle.● Out of box thinking to meet tighter PPA requirements.● Any implementation experience within the field of CPU/GPU IP designs.



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