Physical Design Engineer

1 week ago


Cochin, Kerala, India HCLTech Full time

o Tapeout experience in block level PnR implementation including synthesis for medium to complex blocks

o Good to have experience in TSMC/Intel lower technology node(16/14nm or below)

o Experience in independently analyzing/resolving congestion, timing issues and basic understanding of clock tree build

o Basic Timing understanding to independently analyze timing paths

o Experience in ICC2/Innovus/DC tools, Fusion compiler being added advantage

o Basic equivalency check understanding. Good to have Conformal LEC experience.

o Should have understanding of basic shell scripting, tool based TCL scripting to automate redundant tasks



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