Senior logic design engineer – core units(front end pipeline)

1 day ago

Ellore, Andhra Pradesh, India Mulya Technologies Full time

SENIOR LOGIC DESIGN ENGINEER – Core Units(Front End Pipeline)Fortune 100 OrganizationLocation: BangaloreIntroductionAs a Hardware Developer you'll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable ourcustomers to make better decisions quicker on the most trusted hardware platform in today's market.Your Role And ResponsibilitiesLead the architecture, design and development of Processor Core Frontend of pipeline units for high-performance Systems. Architect and design I-Cache, Instruction Fetch, Branch Prediction andDecode units of a high performance processor CPU Develop the features, present the proposed architecture in the High leveldesign discussions Estimate the overall effort to develop the feature. Estimate silicon area and wire usage for the feature. Develop micro-architecture, Design RTL, Collaborate with other Coreunits, Verification, DFT, Physical design, Timing, FW, SW teams to developthe feature Signoff the Pre-silicon Design that meets all the functional, area andtiming goals Participate in post silicon lab bring-up and validation of the hardware Lead a team of engineers, guide and mentor team members, representas Logic Design Lead in global forums.Preferred EducationDoctorate DegreeRequired Technical And Professional Expertise8 or more years of demonstrated experience in architecting anddesigning specific CPU unit(eg. I-Cache, Instruction Fetch, BranchPrediction, Instruction Decode) Hands on experience of different Branch Prediction techniques Deep expertise in Out of Order, Super Scalar, Multi-Threaded CoreArchitecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86,ARM, or RISC-V processor designs) Proficiency of RTL design with Verilog or VHDL Knowledge of at least one object oriented or functional programminglanguage and scripting language. Nice to haves Knowledge of instruction decode and handling pipeline hazards Knowledge of verification principles and coverage High-level knowledge of Linux operating system Understanding of Agile development processes Experience with Dev Ops design methodologies and tools Required ContactUdayMulya

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