Job Description

- Make ASIC / SoC / IP core techno commercial plan, design documents, integration guidelines for Digital as well as Mixed Signal chip.

- Write RTL code (Verilog or SystemVerilog)

- Make IP configuration and generate RTL if the IP is provided from other vendors.

- Integrate IP into block, then release RTL to build SoC.

- Cooperate with Verification Team to qualify the design.

- Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create architecture and micro-architecture with detailed design documents for some of the components of the design for medium to high complexity functionality.

- Be an individual contributor in the Design Tasks

- RTL coding of design, synthesis, CDC analysis, debug, Test development etc.

- May need to interact with customers to discuss/ understand customers' specification requirements, if needed .

- The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide.

Requirements :

- Seasoned with RTL/logic design flow and basic knowledge such as FSM, combinational logic, sequential logic, FIFO, etc.

- Good understanding of Verilog/SystemVerilog for synthesis

- Good understanding of design techniques such as multi clock domain crossing (CDC), low power, etc.

- Must have 5+ years of relevant experience.

- Knowledge of one or more of protocols: AMBA (AMBA2, AXI), SD-MMC, MIPI-I3C/UFS/Unipro, Ethernet, DDR, PCIe, USB

- Hands on experience with architecting / micro-architecture/ detailed design from Functional Specifications.

- Must have worked on control path oriented designs like asynchronous FIFO, DMA architectures, SPRAM/ DPRAM interface design, etc.

- Hands on experience with Synthesizable Verilog/ System Verilog RTL coding for ASIC designs and Simulation tools

- Lint, CDC, Synthesis flow and static timing flows, Formal checking, etc is a must for candidates with design background.

- Experience with Scatter Gather DMA design, exposure to SPI/I2C/I2S serial controller interface is a significant plus.

- Experience with Git / Perforce or similar revision control environment

- Knowledge of Perl/Shell scripts