Microarchitect & RTL Design Engineer ( Senior Staff / Staff )
1 week ago
Bangalore / Austin / Santa Clara /We are an early stage tech startup based in Silicon Valley, funded by top tier venture and strategic investors. We are a team of seasoned semiconductor and software professionals with track record of building successful products and companies. We have offices in Santa Clara and Bangalore and we are actively hiring to build an exceptional team of engineers, architects and executives. We offer generous cash and equity based compensation, an exciting and flexible work environment, and the opportunity to mingle and work with some of the biggest names in the semiconductor industry. While we are always on the lookout for star engineers who are eager to work at a premier startup to build high impact industry transforming products, following are some of the specific roles that are currently open.
Senior Hardware Design Engineer(US) SANTA CLARA CA, AUSTIN TX, BangaloreHARDWARE ENGINEERING | ON-SITEWe are seeking a seasoned Hardware Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions
ResponsibilitiesDesign and develop microarchitectures for a set of highly configurable IPsMicroarchitecture and RTL coding ensuring optimal performance, power, areaCollaborate with software teams to define configuration requirements, verification collaterals etc.Work with verification teams on assertions, test plans, debug, coverage etc.Qualifications and Preferred SkillsBS, MS in Electrical Engineering, Computer Engineering or Computer Science7+ years and current hands-on experience in microarchitecture and RTL developmentProficiency in Verilog, System VerilogFamiliarity with industry-standard EDA tools and methodologiesExperience with large high-speed, pipelined, stateful designs, and low power designsIn-depth understanding of on-chip interconnects and NoCsExperience with in ARM ACE/CHI or similar coherency protocolsExperience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and NoCsFamiliarity with RAS designs, QoS in fabrics, PCIe/IO is a plusExperience with modern programming languages like Python is a plusExcellent problem-solving skills and attention to detailStrong communication and collaboration skills
Contact: UdayMulya TechnologiesEmail:
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Greater Bengaluru Area, India Mulya Technologies Full timeMicroarchitect & RTL Design Engineer ( Staff / Senior Engineer ) Bangalore / Austin / Santa Clara /We are an early stage tech startup based in Silicon Valley, funded by top tier venture and strategic investors. We are a team of seasoned semiconductor and software professionals with track record of building successful products and companies. We have offices...
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