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Bangalore City, India Wipro Full timeAbout the Company Wipro Hiring - Senior Physical Design Lead. About the Role Experience: 7+ Yrs PFB JD: In-depth knowledge and hands-on experience on Netlist2 GDSII Implementation i. E. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experience on Physical Design Methodologies and sub-micron...
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Senior Physical Design Engineer
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bangalore, India Wipro Full timeSenior Physical Design Engineer: Exp-6+yrsKEY RESPONSIBILITIES:Lead the team responsible for Synthesis, Physical Design, timing and Physical closureManage a large team of internal and external resourcesResponsible for ensuring the completion of the SOC chip on schedule with high QORPhysical implementation of block level and subsystem levelContribute to...
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Senior Physical Design Engineer
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bangalore, India eInfochips (An Arrow Company) Full timeJob Role: Physical Design Engineer- Senior/Lead Location: Bangalore, Hyderabad, Noida and Ahmedabad Experience Required: 5+ ROLE & RESPONSIBILITIES Engineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal...
Senior Physical Design Lead Engineer
2 months ago
Role Overview:Job Title : PNR LeadExperience : 8+ YearsWork location : BangaloreJob Description:Technical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure Responsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM Must have participated in all stages of the design (floor planning, placement, CTS, routing, physical verification, IREM) Well versed with the timing closure (STA), timing closure methodologies Good Understanding of DRC, LVS,ERC and PERC rule files for lower tech node layout verification Experience in lower tech node (< 7nm) Good automation skills in PERL, TCL and EDA tool-specific scripting Able to take complete ownership for Block/sub-system for complete execution cycle Out of box thinking to meet tighter PPA requirements
