Senior Engineer
1 month ago
Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience in Physical Design Methodologies and sub-micron technology of 16nm and lower technology nodesShould have experience in handling >1M instance count, 1 GHz frequency designsShould have experience in programming in Tcl/Tk/Perl to automate the design process and improve efficiencyMust have hands-on experience on PNR Suite from Cadence & Synopsys (Innovus & ICC2)Strong experience in Static Timing Analysis (PrimeTime – SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre).
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