Senior/lead engineer

1 week ago

Hyderabad, India Silicon Labs Full time

We are Silicon Labs. We are the leading provider of silicon, software and solutions for a smarter, more connected world. We hire the most innovative talent in the world to solve the industry’s toughest problems, providing our customers with significant advantages in performance, energy savings, connectivity and design simplicity. Silicon Labs’ software and mixed signal engineering teams create solutions for customers in diverse markets including the Internet of Things, (Io T), internet infrastructure, TV tuners, as well as automotive and consumer radios. Our solutions are in products from the market leaders in home automation, electric vehicles, green technology, smart TVs and home voice control automation. We take pride in our products and in our people, and that’s one of the many reasons we continue to be awarded Most Respected Public Semiconductor Company by the Global Semiconductor Alliance Job Description: Person will be responsible for driving DFT implementation in Wireless So C chips. The person will have full ownership of ATPG architecture, design, implementation, verification and deployment to Silicon testing, working with Test engineer. The responsibilities also include MBIST design, implementation and verification for all memories in the So C. Person should be capable of generate and debug DFT patterns on tester. Work closely with the design, design-verification, and backend teams to enable the integration an validation of the test logic in all phases of the design, and backend implementation flow. Experience Level: 5+ years Education Requirements: B. Tech/M. Tech in ECE, EEE Minimum Qualifications: Full-chip DFT working experience with multiple design Tape Outs Expert knowledge of DFT architecture on complex Design with multiple clock domains. Experience in ATPG for pattern generation and simulation of Test Transition faults, Stuck-at, IDDQ, at-speed faults. Hands-on experience in industry standard DFT tools - Mentor Tessent suite or Synopsys DFT compiler. Block level and Chip level SCAN insertion, DRC, Coverage Analysis and improvements. Expertise in Scan Compression(EDT/OPMISR+), MBIST, ATPG implementation and verification. Expert knowledge on Test time reduction. Good Knowledge of cross functional domains (SYN, LEC, STA, PD) with owner ship of constraints developments & LEC. Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process Experience working with cross functional global teams Experience in Low-Power DFT requirements. Experience in Low-Power MBIST architectures and Memory testing. Preferred Qualifications: Experience in DFT related RTL integration. Excellent communication and analytical skills Experience in leading junior teams, Mentoring/Training and Project leadership. Exceptional problem-solving skills Benefits & Perks: Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs) Employee Stock Purchase Plan (ESPP) Insurance plans with Outpatient cover National Pension Scheme (NPS) Flexible work policy Childcare support

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