Senior RTL Design Engineer

2 days ago

bangalore, India TekPillar® Full time

Job Title: Senior RTL Design Engineer Experience: 5 to 8 Years Location: Noida & Ahmedabad Key Responsibilities: Design, develop, and verify FPGA modules using Verilog RTL . Perform synthesis, simulation, and timing closure using Xilinx Vivado . Work on Zynq UltraScale+ FPGA platforms and integrate peripherals: I2C, SPI, DDR, EMMC, AMBA, PL, PS . Collaborate with cross-functional teams for end-to-end design delivery. Required Skills: 5+ years of hands-on RTL/FPGA design experience. Proficiency in Xilinx Vivado and FPGA design flows. Strong understanding of FPGA architecture, synthesis, and timing closure . Experience with Zynq UltraScale+ family and interfacing protocols. Nice to Have: High-speed digital design experience. Knowledge of HDMI interface .

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