Senior Physical Design Engineer
3 weeks ago
Perform subsystem-level floor planning, placement, and routing for high-performance microprocessor design.
Collaborate with cross-functional teams to achieve design goals.
Close the design to meet timing, power, and area requirements.
Implement engineering change orders (ECOs) to rectify functional bugs and timing issues.
Ensure the quality and efficiency of the RTL to GDS implementation process.
Required Technical and Professional Expertise:
-- years of industry experience
-Strong knowledge and hands-on experience in physical design, timing, and methodology, including logic synthesis, placement, clock tree synthesis, routing, and post--route closure.
-Proficiency in physical verification (LVS, DRC, etc.), noise analysis, power analysis, and electro-migration.
-Solid experience in static timing analysis (closing timing at the chip level).
-Good understanding of timing constraints.
-Experience in handling asynchronous timing and multiple corner timing closure.
Preferred Technical and Professional Experience:
Automation skills in PERL, SKILL, and/or TCL
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