Senior/lead Asic/ip Verification Engineers
1 week ago
Job Title: Senior/Lead/Architect PCIE Verification Engineer
About the RoleWe are seeking experienced professionals to join our Bangalore and Noida teams as Senior/Lead/Architect PCIE Verification Engineers.
Responsibilities- Contribute to the development of Verification Intellectual Property (VIP)
- Review and sign-off VIP development and updates from a technical perspective, including methodology and protocol functional prospective
- Define test plans for PCIe specification features, develop sequences, and test cases
- Ensure validation completeness through regression stability and coverage convergence
- 4-15 years of experience in R&D Engineering with multiple level roles
- Hands-on experience with System Verilog and Verilog
- Good understanding of Object Oriented Programming
- Experience with PCIe protocol, preferably the latest specifications like PCIe Gen6
- Involvement in reusable verification environments using VMM/OVM/UVM methodologies
- Liaison with Architects/methodology experts to achieve resolutions on issues or drive output from an architecture/methodology perspective
Synopsys is an equal opportunities employer and considers all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.
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