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Staff Design Engineer

1 month ago

Bengaluru, India Ananant Systems Private Limited Full time
Vision:
Establishing a world-class semiconductor and wireless systems company headquartered in India to address the expanding requirements for advanced connectivity, computing, and security for wireless 5G and 6G infrastructure and devices. Our product offerings including Intellectual Property (IP), chip design, semiconductor products, software and systems developed and owned in India. Drawing inspiration from industry giants like Qualcomm and MediaTek, we aim to become the leader in wireless semiconductor and systems player in India and worldwide.
Key Points:
Atmanirbhar Approach: All intellectual property (IP) owned within India.
National Security: Sovereign infrastructure, using secure chips and systems.
Cost Efficiency: Offering solutions at one-third the cost of current wireless alternatives, providing superior technology at a more affordable price compared to Chinese counterparts such as Huawei.
Global Market Reach: Products proudly made in India to cater to the global market, reflecting a commitment to excellence and competitiveness on a global scale.
Ecosystem Alignment: Collaborate with semiconductor and systems manufacturing partners in India to develop indigenous telecom infrastructure/ devices.
Responsibilities: -
Ananant Systems is developing an advanced RISC-V based, state of the art multi-core architecture, with associated memory and NOC subsystems, complex data processing subsystems and high speed interconnects (PCIE,Ethernet,JESD) targeted for 5G physical layer signal processing.
The FPGA implementation/validation engineer in the team will have ownership of mapping the design at unit and at full chip level onto FPGA and work with either standalone or interface with other FPGA platforms.
The engineer will
plan and execute unit and cluster level implementation of RTL, develop the wrapper logic, map the design onto the state of the art FPGA platforms and ensure that the design is meets the quality and performance.
Will be responsible for developing testbench in SV/UVM to verify the sanity of the design prior to the FPGA testing.
work with architects to understand and influence the unit's architecture, plan and implement design changes in Verilog or SV, plan and implement verification environment in UVM, and execute the verification plan until all quality criteria are met.
FPGA Engineer ( FPGA Design)
PhD / Masters / Bachelors Degree in Electronics or Computer Engineering
5 + yrs Industry experience
Design/RTL experience in Verilog or SV is a must.
Proficient in FPGA tools such as Synplicity, Xilinx Vivado and ChipScope usage ( Experience with one of MPSOC, RFSOC, Ultrascale devices is required)
Experience in FPGA timing constraints, timing analysis, clock domain crossing.
Experience of timing closure of large designs requiring > 200 MHz clock frequency and high fpga utilization
Domain knowledge in Digital Baseband Hardware / Signal Processing for LTE / 5G / WLAN is desirable