Principal Analog Design Engineer
2 weeks ago
The Opportunity
We're looking for the Wavemakers of tomorrow.
We enable tomorrow's future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product progress in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission- critical data communication, our technologies, and our track record. Together, we enable the next generation of digital technology.
Our unique, DSP-based, multi-standard connectivity Silicon IP solutions use years of experience and Ramp to build the most power-efficient solution available on the market to enable devices of the future
What You'll do:
D2D/UCIe/HBM/DDR interface sub-block design such as DLL, PLL, High Speed IO and high-speed custom logic designs
Define Block-level architecture and circuit topologies to meet system spec.
Circuit Design and simulation across PVT and sign off quality matrix to meet specs
Mentor the junior designers and support them in problem solving
Support .lib generation and Verilog modelling for block owned and validate with schematic
Custom Layout guidelines and post-layout simulations
Documentation, Review and Signoff on design
What You'll Need:
Minimum 12 years of experience in Analog circuit design from a reputed product-based company
Experience in dual patterning FinFET design in in TSMC 3nm, 5nm, 7nm, 16ffc, Samsung 3/5nm
Experience designing circuit at 10-32 Gbps speed
Understanding of device basics and physics, with an understanding of the following:
High speed Driver and Receiver designs, PLL design with solid system understanding
Hands-on experience of Sub block design of Current mirrors, bandgap reference, Opamp, amplifiers with small-signal analysis of several topologies
Proved track record of delivering high speed, high precision circuits for leading SoC designs
Basic knowledge of the following layouts: antenna checks, antenna failure, latchup issues, ESD constraints, and layout rules, ERC related checks, matching, cross talk, coupling, shielding, guard ring usage, LEF generation, .lib characterization, extraction setup, DRC LVS runs switch knowledge, IR drop requirements, EM issues, parasitic matching, parasitic reduction techniques, and static and dynamic IR analysis
Experience in ADC/DAC/Regulator or High Speed SerDes circuit design
BTech/MTech/MS in VLSI from a reputed university
you will be reporting to Director Analog Design
"Hybrid work environment"
As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes:
Competitive Compensation Package
Restricted Stock Units (RSUs)
Hybrid Working Model
Provisions to pursue advanced education from Premium Institute, eLearning content providers
Medical Insurance and a cohort of Wellness Benefits
Educational Assistance
Advance Loan Assistance
Office lunch & Snacks Facility
Contact:
Uday
Mulya Technologies
"Mining The Knowledge Community"
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