Senior Engineer, Digital Design Engineering
2 weeks ago
BangaloreResponsibilities:Collaborate with the design team to ensure efficient and effective testability of complex integrated circuits.Design and implement DFT features such as scan chains, compression, and built-in self-test structures to enhance testability.Conduct DFT DRC checks in RTL/Netlist database to ensure compliance with DFT guidelines and rules.Utilize Cadence/Siemen’s DFT tool to perform DFT analysis and optimize testability metrics.Generating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models using on-chip test compression techniques.MBIST Design (including repair) and Verification using Siemen’s EDA tool.Validation of DFT structures/patterns in RTL, Netlist with and without SDF.Work closely with the verification team to define and implement DFT verification plans.Work closely with physical design team for DFT implementation/constraints strategy for synthesis/STA.Analyze and debug test failures and collaborate with the test engineering team to resolve issues.Provide guidance and mentorship to junior DFT engineers.Qualifications:Bachelor's/Master's degree in Electrical/Electronic Engineering, or a related field.4-10 years of hands-on experience in DFT methodologies and techniques.Strong knowledge of LBIST, ATPG, DFT DRC, Scan compression, Low power DFT Techniques, MBIST, Boundary Scan, Analog DFT, JTAG Architecture, DFT STA Constraint development.Hand-on experience/expertise in Cadence/Siemen’s DFT EDA tools for Scan stitching, DRC, ATPG, Coverage improvement, MBIST, Boundary Scan.Proficiency in scripting languages such as Perl, Tcl, and/or Python for automation.Solid understanding of digital design fundamentals, RTL coding, Lint/CDC, Low Power Checks and ASIC design flow.Excellent problem-solving skills and ability to work effectively in a team-oriented environment.Strong communication and interpersonal skills.Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days
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Senior Digital Design Engineer
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Senior Digital Design Engineer
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Design Engineer
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Senior Physical Design Engineer
2 months ago
Greater Bengaluru Area, India ACL Digital Full timeACL Digital is hiring for PD and STA Engineers for Bangalore and Hyderabad Locations.3+years experience in Physical Design.Must have exp into floorplanning, STA blocks (2 blocks each) from synthesis, PnR, Timing and PV closure.
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Senior Physical Design Engineer
2 months ago
Greater Bengaluru Area, India ACL Digital Full timeACL Digital is hiring for PD and STA Engineers for Bangalore and Hyderabad Locations. 3+years experience in Physical Design. Must have exp into floorplanning, STA blocks (2 blocks each) from synthesis, PnR, Timing and PV closure.