Associate Engineer, Layout
3 weeks ago
development for Power Management blocks & standard cells.Take complete ownership of Assigned Layout tasks.Responsible for on-time delivery of block-level layoutsOptimizing the layouts based on performance and Area.Verify and clean DRC/LVS/ERC/ANT checks for layouts.Ability to understand design constraints and implement high-quality layouts.Competency RequirementsIn order to perform the job successfully, an individual should demonstrate the following competencies:Critical Thinking : Skilled at finding logical flaws in arguments and plans; identifies problems and solutions that others might miss; provides detailed insight and constructive criticism into problems and complex situationsWorking with Ambiguity : Achieves forward progress in the face of poorly defined situations and/or unclear goals; able to work effectively with limited or partial informationServing Customers : Builds strong relationships with customers; stays aware of customer needs, concerns and satisfaction; responds promptly to customer questions and requests; effectively manages customer expectationsAdapting to Change : Maintains a positive attitude in the face of change; appropriately adjusts behavior and activities to changing conditionsDelivering High Quality Work : Critically reviews work processes to ensure quality; addresses problems that could impact quality; makes sure project deliverables and services meet all requirements and expectations; does not make the same mistakes twice
Minimum Qualifications (Experience and Skills):0-1 year of related Analog Layout experience.Should have knowledge of device physics and process/fabrication technology.Good understanding of Analog Layout fundamentals.Understanding of Deep Submicron issues and layout techniques.Working knowledge in Cadence Virtuoso for layout development and PVS/Calibre for Physical Verification checks.Should have knowledge in layout matching, DRC, LVS and ERC checks.Familiarity with CMOS and BCD process and IC development process.Excellent verbal and written communication skills.Exceptional collaboration and communication skills across distributed teams.
Education Requirements:Bachelor's or Master's Degree in Electrical/Electronics Engineering
Work EnvironmentThis job operates in a professional office environment. This role routinely uses standard office equipment.Physical DemandsThe physical demands described here are representative of those that must be met by an employee to successfully perform the essential functions of this job. While performing the duties of this job, the employee is regularly required to talk or hear. The employee frequently is required to stand; walk; use hands to finger, handle or feel; and reach with hands and arms. Specific vision abilities required by this job include close vision, distance vision, color vision, peripheral vision, depth perception and ability to adjust focus. This position requires the ability to occasionally lift office products and supplies, up to 20 pounds.
pSemi Corporation supports a diverse workforce and is committed to a policy of equal employment opportunity for applicants and employees. pSemi does not discriminate on the basis of age, race, color, religion (including religious dress and grooming practices), sex/gender (including pregnancy, childbirth, or related medical conditions or breastfeeding), gender identity, gender expression, genetic information, national origin (including language use restrictions and possession of a driver’s license issued under Vehicle Code section 12801.9), ancestry, physical or mental disability, legally-protected medical condition, military or veteran status (including “protected veterans” under applicable affirmative action laws), marital status, sexual orientation, or any other basis protected by local, state or federal laws applicable to the Company. pSemi also prohibits discrimination based on the perception that an employee or applicant has any of those characteristics, or is associated with a person who has or is perceived as having any of those characteristics.Note: The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are registered trademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries. All other trademarks are the property of their respective companies. pSemi products are protected under one or more of the following U.S. Patents:
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