CPU Design Verification Engineer
2 weeks ago
CPU Test Bench DV Engineer
ResponsibilitiesDesign, develop, and maintain parameterizable core and cluster testbench environments (C++ and Synthesizable SV) for a RISCV CPU familyBuild key testbench components including harnesses, checkers, transactors, models and miscellaneous items like preloaders, trickbox, randomization etcContribute to C++ methodology framework that incorporates modern C++ features, to ease writing of testbench components - CVM (UVM for C++)Work with environments that are portable across simulators (including open source verilator) and emulation platformsSupport the core and cluster DV teams with bringing up arch and micro-arch featuresDevelop tools and innovative solutions to simplify debug of simulation/emulation failuresExperience and QualificationsBachelors/Masters in ECE/CS with at least 7 years of experienceProficiency in C++ and SV programming languagesGood understanding of the fundamentals behind a DV methodology like UVMGood understanding of software engineering concepts, like publisher-subscriber patterns, multi-threaded programming, co-routines, etcKnowledge of any CPU architecture (x86, ARM, RISCV) and basic micro-architectureSolid problem-solving skills and the ability to analyze across layers of abstraction stack from high level software code to low level assembly programs to RTL implementation codeExcellent communication skills and the ability to work effectively in a team environmentEagerness to learn and adapt to new challenges in a fast-paced, dynamic environment
Locations:
Bangalore, India
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
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