Senior Design Verification Engineer
7 hours ago
ROLE & RESPONSIBILITIES
An expert level with developing UVM-based SV test-benches.
Highly experienced with defining block, sub-system and SOC top level test plans.
Relevant experience with one or more of PCIe, NVMe, NAND, DDR and CPU sub-systems.
Deep understanding and knowledge of verification methodologies, flows and quality metrics
The incumbent will be responsible for executing complete verification project in the role senior engineer with hands on experience, mentoring, client communication / interactions, in-depth technical reviews, and close tracking of technical as well as management aspect
ESSENTIAL SKILLS & EXPERIENCE
At-least 4 years of experience in System Verilog HVL.
At-least 3 year of experience in OVM/UVM/VMM/Test Harness.
Hands on experience of developing assertion, checkers, coverage and scenario creation.
Must have executed at-least 1 SoC Verification project
Experience in developing test and coverage plan, Verification environment and validation plan.
Knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required.
EDUCATION BACKGROUND
B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering.
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